Simulation Results: aes/masked

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.35 %
  • code
  • 94.68 %
  • assert
  • 98.23 %
  • func
  • 75.14 %
  • block
  • 94.99 %
  • line
  • 95.96 %
  • branch
  • 89.31 %
  • toggle
  • 97.90 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 237.608us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 102.642us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 84.470us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 62.459us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 1104.977us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 94.996us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 78.208us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 62.459us 1 1 100.00
aes_csr_aliasing 3.000s 94.996us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 102.642us 1 1 100.00
aes_config_error 3.000s 139.478us 1 1 100.00
aes_stress 3.000s 84.988us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 102.642us 1 1 100.00
aes_config_error 3.000s 139.478us 1 1 100.00
aes_stress 3.000s 84.988us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 84.988us 1 1 100.00
aes_b2b 10.000s 1115.211us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 84.988us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 102.642us 1 1 100.00
aes_config_error 3.000s 139.478us 1 1 100.00
aes_stress 3.000s 84.988us 1 1 100.00
aes_alert_reset 2.000s 135.477us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 122.450us 1 1 100.00
aes_config_error 3.000s 139.478us 1 1 100.00
aes_alert_reset 2.000s 135.477us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 119.175us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 6.000s 611.593us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 135.477us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 84.988us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 84.988us 1 1 100.00
aes_sideload 3.000s 118.816us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 227.339us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 12.000s 1307.384us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 53.685us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 236.926us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 236.926us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 84.470us 1 1 100.00
aes_csr_rw 1.000s 62.459us 1 1 100.00
aes_csr_aliasing 3.000s 94.996us 1 1 100.00
aes_same_csr_outstanding 2.000s 57.983us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 84.470us 1 1 100.00
aes_csr_rw 1.000s 62.459us 1 1 100.00
aes_csr_aliasing 3.000s 94.996us 1 1 100.00
aes_same_csr_outstanding 2.000s 57.983us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 4.000s 474.537us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 5.000s 336.696us 0 1 0.00
aes_control_fi 2.000s 52.843us 1 1 100.00
aes_cipher_fi 3.000s 62.894us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 306.217us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 306.217us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 306.217us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 306.217us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 172.985us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 485.739us 1 1 100.00
aes_tl_intg_err 3.000s 322.134us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 322.134us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 135.477us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 306.217us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 306.217us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 102.642us 1 1 100.00
aes_stress 3.000s 84.988us 1 1 100.00
aes_alert_reset 2.000s 135.477us 1 1 100.00
aes_core_fi 4.000s 214.908us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 139.478us 1 1 100.00
aes_stress 3.000s 84.988us 1 1 100.00
aes_core_fi 4.000s 214.908us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 306.217us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 4.000s 280.170us 1 1 100.00
aes_stress 3.000s 84.988us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 84.988us 1 1 100.00
aes_sideload 3.000s 118.816us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 4.000s 280.170us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 4.000s 280.170us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 4.000s 280.170us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 4.000s 280.170us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 4.000s 280.170us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 84.988us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 84.988us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 5.000s 336.696us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 5.000s 336.696us 0 1 0.00
aes_control_fi 2.000s 52.843us 1 1 100.00
aes_cipher_fi 3.000s 62.894us 1 1 100.00
aes_ctr_fi 2.000s 72.994us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 5.000s 336.696us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 5.000s 336.696us 0 1 0.00
aes_control_fi 2.000s 52.843us 1 1 100.00
aes_cipher_fi 3.000s 62.894us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 62.894us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 5.000s 336.696us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 5.000s 336.696us 0 1 0.00
aes_control_fi 2.000s 52.843us 1 1 100.00
aes_ctr_fi 2.000s 72.994us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 5.000s 336.696us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 5.000s 336.696us 0 1 0.00
aes_control_fi 2.000s 52.843us 1 1 100.00
aes_cipher_fi 3.000s 62.894us 1 1 100.00
aes_ctr_fi 2.000s 72.994us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 135.477us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 5.000s 336.696us 0 1 0.00
aes_control_fi 2.000s 52.843us 1 1 100.00
aes_cipher_fi 3.000s 62.894us 1 1 100.00
aes_ctr_fi 2.000s 72.994us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 5.000s 336.696us 0 1 0.00
aes_control_fi 2.000s 52.843us 1 1 100.00
aes_cipher_fi 3.000s 62.894us 1 1 100.00
aes_ctr_fi 2.000s 72.994us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 5.000s 336.696us 0 1 0.00
aes_control_fi 2.000s 52.843us 1 1 100.00
aes_ctr_fi 2.000s 72.994us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 5.000s 336.696us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 5.000s 336.696us 0 1 0.00
aes_control_fi 2.000s 52.843us 1 1 100.00
aes_cipher_fi 3.000s 62.894us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 8.000s 378.077us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
aes_reseed 57356161630526292970231708877205350127982294494623681186577442837658927601715 10260
UVM_INFO @ 474536860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 88402146065439762431534721068659265781585755295102161806813228880297794252020 17380
UVM_INFO @ 1307383816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 58015288551066913441863932380447782818516451617568787603288340950571919250731 316
UVM_INFO @ 378077426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 22619537638387216692631245036887014834111821505926593229206629450342256656123 26608
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0