Simulation Results: aes/unmasked

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.78 %
  • code
  • 90.09 %
  • assert
  • 97.73 %
  • func
  • 75.53 %
  • block
  • 89.85 %
  • line
  • 92.26 %
  • branch
  • 81.22 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 76.266us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 81.861us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 68.142us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 3.000s 184.052us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 9.000s 160.262us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 4.000s 1037.159us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 69.646us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 3.000s 184.052us 1 1 100.00
aes_csr_aliasing 4.000s 1037.159us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 81.861us 1 1 100.00
aes_config_error 3.000s 163.809us 1 1 100.00
aes_stress 2.000s 63.850us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 81.861us 1 1 100.00
aes_config_error 3.000s 163.809us 1 1 100.00
aes_stress 2.000s 63.850us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 63.850us 1 1 100.00
aes_b2b 6.000s 421.690us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 63.850us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 81.861us 1 1 100.00
aes_config_error 3.000s 163.809us 1 1 100.00
aes_stress 2.000s 63.850us 1 1 100.00
aes_alert_reset 3.000s 140.679us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 53.577us 1 1 100.00
aes_config_error 3.000s 163.809us 1 1 100.00
aes_alert_reset 3.000s 140.679us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 123.980us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 400.459us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 140.679us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 63.850us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 63.850us 1 1 100.00
aes_sideload 2.000s 290.546us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 341.513us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 9.000s 210.687us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 3.000s 53.434us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 99.815us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 99.815us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 68.142us 1 1 100.00
aes_csr_rw 3.000s 184.052us 1 1 100.00
aes_csr_aliasing 4.000s 1037.159us 1 1 100.00
aes_same_csr_outstanding 3.000s 336.146us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 68.142us 1 1 100.00
aes_csr_rw 3.000s 184.052us 1 1 100.00
aes_csr_aliasing 4.000s 1037.159us 1 1 100.00
aes_same_csr_outstanding 3.000s 336.146us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 1.000s 12.818us 0 1 0.00
fault_inject 1 3 33.33
aes_fi 3.000s 194.814us 0 1 0.00
aes_control_fi 17.000s 10004.199us 0 1 0.00
aes_cipher_fi 2.000s 53.380us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 205.450us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 205.450us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 205.450us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 205.450us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 82.248us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 859.576us 1 1 100.00
aes_tl_intg_err 2.000s 324.779us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 324.779us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 140.679us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 205.450us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 205.450us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 81.861us 1 1 100.00
aes_stress 2.000s 63.850us 1 1 100.00
aes_alert_reset 3.000s 140.679us 1 1 100.00
aes_core_fi 2.000s 76.452us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 163.809us 1 1 100.00
aes_stress 2.000s 63.850us 1 1 100.00
aes_core_fi 2.000s 76.452us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 205.450us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 63.143us 1 1 100.00
aes_stress 2.000s 63.850us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 63.850us 1 1 100.00
aes_sideload 2.000s 290.546us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 63.143us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 63.143us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 63.143us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 63.143us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 63.143us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 63.850us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 63.850us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 194.814us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 3.000s 194.814us 0 1 0.00
aes_control_fi 17.000s 10004.199us 0 1 0.00
aes_cipher_fi 2.000s 53.380us 1 1 100.00
aes_ctr_fi 1.000s 82.664us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 194.814us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 3.000s 194.814us 0 1 0.00
aes_control_fi 17.000s 10004.199us 0 1 0.00
aes_cipher_fi 2.000s 53.380us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 53.380us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 194.814us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 3.000s 194.814us 0 1 0.00
aes_control_fi 17.000s 10004.199us 0 1 0.00
aes_ctr_fi 1.000s 82.664us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 194.814us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 3.000s 194.814us 0 1 0.00
aes_control_fi 17.000s 10004.199us 0 1 0.00
aes_cipher_fi 2.000s 53.380us 1 1 100.00
aes_ctr_fi 1.000s 82.664us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 140.679us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 3.000s 194.814us 0 1 0.00
aes_control_fi 17.000s 10004.199us 0 1 0.00
aes_cipher_fi 2.000s 53.380us 1 1 100.00
aes_ctr_fi 1.000s 82.664us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 3.000s 194.814us 0 1 0.00
aes_control_fi 17.000s 10004.199us 0 1 0.00
aes_cipher_fi 2.000s 53.380us 1 1 100.00
aes_ctr_fi 1.000s 82.664us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 3.000s 194.814us 0 1 0.00
aes_control_fi 17.000s 10004.199us 0 1 0.00
aes_ctr_fi 1.000s 82.664us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 194.814us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 3.000s 194.814us 0 1 0.00
aes_control_fi 17.000s 10004.199us 0 1 0.00
aes_cipher_fi 2.000s 53.380us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 8.000s 397.810us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 114761109253941084725759324359612572709065430783837878701200860196546775930356 1455
UVM_INFO @ 12817959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 74335419237684456311930014215891133576042531061682721193103058966019722734510 464
UVM_INFO @ 397809764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 7604323561177737141541971312212002050513906059189302280839487539725524463981 8488
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 1 test run
aes_control_fi 47385437596749595353563143515237657502539890081210882498465580895155572217853 146
UVM_INFO @ 10004198840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---