Simulation Results: clkmgr

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.11 %
  • code
  • 97.45 %
  • assert
  • 93.64 %
  • func
  • 85.25 %
  • line
  • 98.88 %
  • branch
  • 98.43 %
  • cond
  • 89.92 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.010s 57.010us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.810s 37.966us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.710s 16.049us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.660s 292.336us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.180s 82.614us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.070s 102.482us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.710s 16.049us 1 1 100.00
clkmgr_csr_aliasing 1.180s 82.614us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.680s 17.576us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.880s 19.651us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.080s 232.412us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.680s 19.871us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.010s 57.010us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 10.520s 2359.358us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 2.280s 785.194us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 10.520s 2359.358us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 18.710s 7594.232us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.790s 16.780us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.200s 978.297us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.200s 978.297us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.810s 37.966us 1 1 100.00
clkmgr_csr_rw 0.710s 16.049us 1 1 100.00
clkmgr_csr_aliasing 1.180s 82.614us 1 1 100.00
clkmgr_same_csr_outstanding 1.090s 126.007us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.810s 37.966us 1 1 100.00
clkmgr_csr_rw 0.710s 16.049us 1 1 100.00
clkmgr_csr_aliasing 1.180s 82.614us 1 1 100.00
clkmgr_same_csr_outstanding 1.090s 126.007us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
clkmgr_sec_cm 1.690s 302.729us 1 1 100.00
clkmgr_tl_intg_err 1.890s 74.844us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 793.660s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 793.660s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 793.660s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 793.660s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 426.060s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.890s 74.844us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 10.520s 2359.358us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 2.280s 785.194us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 793.660s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.930s 71.127us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.780s 29.124us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.720s 37.516us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.770s 42.357us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.740s 42.030us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.710s 16.049us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 1.690s 302.729us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.710s 16.049us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.710s 16.049us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 1.690s 302.729us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 5.070s 1093.909us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 39.310s 4111.661us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
clkmgr_shadow_reg_errors 61864311183426421595635125865127997456657721199812958023548172559813058122791 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 85133287746494960792271034628133292050964805544032419904149371219656957800270 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---