Simulation Results: csrng

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 76.68 %
  • code
  • 89.49 %
  • assert
  • 93.67 %
  • func
  • 46.89 %
  • block
  • 95.08 %
  • line
  • 95.71 %
  • branch
  • 88.23 %
  • toggle
  • 88.30 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 83.185us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 54.571us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 20.413us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 27.000s 1286.179us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 58.117us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 96.414us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 20.413us 1 1 100.00
csrng_csr_aliasing 3.000s 58.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 121.171us 1 1 100.00
alerts 1 1 100.00
csrng_alert 3.000s 83.728us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 36.608us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 2.000s 35.015us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 2.000s 35.015us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 12.000s 114.679us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 20.741us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 28.126us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 166.351us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 166.351us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 54.571us 1 1 100.00
csrng_csr_rw 1.000s 20.413us 1 1 100.00
csrng_csr_aliasing 3.000s 58.117us 1 1 100.00
csrng_same_csr_outstanding 2.000s 47.227us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 54.571us 1 1 100.00
csrng_csr_rw 1.000s 20.413us 1 1 100.00
csrng_csr_aliasing 3.000s 58.117us 1 1 100.00
csrng_same_csr_outstanding 2.000s 47.227us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 16.000s 1902.040us 1 1 100.00
csrng_tl_intg_err 2.000s 82.598us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 14.127us 1 1 100.00
csrng_csr_rw 1.000s 20.413us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 3.000s 83.728us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 12.000s 114.679us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 121.171us 1 1 100.00
csrng_err 2.000s 36.608us 1 1 100.00
csrng_sec_cm 16.000s 1902.040us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 121.171us 1 1 100.00
csrng_err 2.000s 36.608us 1 1 100.00
csrng_sec_cm 16.000s 1902.040us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 121.171us 1 1 100.00
csrng_err 2.000s 36.608us 1 1 100.00
csrng_sec_cm 16.000s 1902.040us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 121.171us 1 1 100.00
csrng_err 2.000s 36.608us 1 1 100.00
csrng_sec_cm 16.000s 1902.040us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 121.171us 1 1 100.00
csrng_err 2.000s 36.608us 1 1 100.00
csrng_sec_cm 16.000s 1902.040us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 3.000s 83.728us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 121.171us 1 1 100.00
csrng_err 2.000s 36.608us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 12.000s 114.679us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 3.000s 83.728us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 2.000s 82.598us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 121.171us 1 1 100.00
csrng_err 2.000s 36.608us 1 1 100.00
csrng_sec_cm 16.000s 1902.040us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 121.171us 1 1 100.00
csrng_err 2.000s 36.608us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 121.171us 1 1 100.00
csrng_err 2.000s 36.608us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 121.171us 1 1 100.00
csrng_err 2.000s 36.608us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 121.171us 1 1 100.00
csrng_err 2.000s 36.608us 1 1 100.00
csrng_sec_cm 16.000s 1902.040us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 121.171us 1 1 100.00
csrng_err 2.000s 36.608us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.194s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:667) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 56182527294500843268417046348144759465170353633753175611661908819741330797810 100
UVM_INFO @ 35015378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 19155268240242255569558314882923362000003293963283521500791949654428329794178 None