Simulation Results: edn/edn0

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.65 %
  • code
  • 73.54 %
  • assert
  • 95.01 %
  • func
  • 76.39 %
  • line
  • 95.71 %
  • branch
  • 84.80 %
  • cond
  • 78.41 %
  • toggle
  • 67.92 %
  • FSM
  • 40.86 %
Validation stages
V1
83.33%
V2
85.71%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.960s 18.633us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.770s 22.398us 1 1 100.00
csr_rw 0 1 0.00
edn_csr_rw 105.790s 10000.581us 0 1 0.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.720s 174.809us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.470s 40.849us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.160s 25.471us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
edn_csr_rw 105.790s 10000.581us 0 1 0.00
edn_csr_aliasing 1.470s 40.849us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.000s 74.073us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.000s 74.073us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.000s 74.073us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.950s 24.985us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.100s 148.379us 1 1 100.00
errs 1 1 100.00
edn_err 0.920s 19.957us 1 1 100.00
disable 1 2 50.00
edn_disable 0.840s 39.936us 1 1 100.00
edn_disable_auto_req_mode 0.940s 38.855us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 3.090s 447.915us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.900s 13.708us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.850s 36.961us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.440s 54.986us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.440s 54.986us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
edn_csr_hw_reset 0.770s 22.398us 1 1 100.00
edn_csr_rw 105.790s 10000.581us 0 1 0.00
edn_csr_aliasing 1.470s 40.849us 1 1 100.00
edn_same_csr_outstanding 1.250s 126.721us 1 1 100.00
tl_d_partial_access 3 4 75.00
edn_csr_hw_reset 0.770s 22.398us 1 1 100.00
edn_csr_rw 105.790s 10000.581us 0 1 0.00
edn_csr_aliasing 1.470s 40.849us 1 1 100.00
edn_same_csr_outstanding 1.250s 126.721us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.890s 9587.974us 1 1 100.00
edn_tl_intg_err 1.940s 95.334us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.830s 73.493us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.100s 148.379us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.890s 9587.974us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.890s 9587.974us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.890s 9587.974us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.890s 9587.974us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.100s 148.379us 1 1 100.00
edn_sec_cm 6.890s 9587.974us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.100s 148.379us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.940s 95.334us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 24.410s 5315.108us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (edn_scoreboard.sv:425) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 36004981673261386117649179543860341542146802415050701534763012045438182721626 94
UVM_INFO @ 38855150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_csr_rw 71366409630299000196842056677182965053801923068210891968706175736920196330174 89
UVM_INFO @ 10000580862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---