Simulation Results: edn/edn1

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.16 %
  • code
  • 85.10 %
  • assert
  • 98.70 %
  • func
  • 80.67 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 91.54 %
  • toggle
  • 95.70 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.820s 31.163us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.820s 52.035us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 29.475us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.900s 620.622us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.970s 50.126us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.150s 43.453us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 29.475us 1 1 100.00
edn_csr_aliasing 0.970s 50.126us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.270s 64.071us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.270s 64.071us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.270s 64.071us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.850s 22.535us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.200s 30.726us 1 1 100.00
errs 1 1 100.00
edn_err 0.780s 30.981us 1 1 100.00
disable 2 2 100.00
edn_disable 0.770s 35.585us 1 1 100.00
edn_disable_auto_req_mode 0.960s 131.364us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.750s 218.540us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 13.268us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.900s 20.982us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.190s 311.047us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.190s 311.047us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.820s 52.035us 1 1 100.00
edn_csr_rw 0.770s 29.475us 1 1 100.00
edn_csr_aliasing 0.970s 50.126us 1 1 100.00
edn_same_csr_outstanding 0.860s 21.235us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.820s 52.035us 1 1 100.00
edn_csr_rw 0.770s 29.475us 1 1 100.00
edn_csr_aliasing 0.970s 50.126us 1 1 100.00
edn_same_csr_outstanding 0.860s 21.235us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.910s 1440.947us 1 1 100.00
edn_tl_intg_err 1.250s 72.451us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.770s 39.616us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.200s 30.726us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.910s 1440.947us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.910s 1440.947us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.910s 1440.947us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.910s 1440.947us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.200s 30.726us 1 1 100.00
edn_sec_cm 3.910s 1440.947us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.200s 30.726us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.250s 72.451us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 41.130s 9155.034us 1 1 100.00