| V1 |
|
83.33% |
| V2 |
|
93.75% |
| V2S |
|
85.71% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| entropy_src_smoke | 3.000s | 31.807us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| entropy_src_csr_hw_reset | 1.000s | 20.389us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| entropy_src_csr_rw | 1.000s | 104.785us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| entropy_src_csr_bit_bash | 10.000s | 15781.706us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| entropy_src_csr_aliasing | 2.000s | 109.122us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| entropy_src_csr_mem_rw_with_rand_reset | 1.000s | 9.189us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| entropy_src_csr_rw | 1.000s | 104.785us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 2.000s | 109.122us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 2 | 3 | 66.67 | |||
| entropy_src_smoke | 3.000s | 31.807us | 1 | 1 | 100.00 | |
| entropy_src_rng | 198.000s | 13091.857us | 1 | 1 | 100.00 | |
| entropy_src_fw_ov | 3601.000s | 0.000us | 0 | 1 | 0.00 | |
| firmware_mode | 0 | 1 | 0.00 | |||
| entropy_src_fw_ov | 3601.000s | 0.000us | 0 | 1 | 0.00 | |
| rng_mode | 1 | 1 | 100.00 | |||
| entropy_src_rng | 198.000s | 13091.857us | 1 | 1 | 100.00 | |
| rng_max_rate | 1 | 1 | 100.00 | |||
| entropy_src_rng_max_rate | 93.000s | 14155.494us | 1 | 1 | 100.00 | |
| health_checks | 1 | 1 | 100.00 | |||
| entropy_src_rng | 198.000s | 13091.857us | 1 | 1 | 100.00 | |
| conditioning | 1 | 1 | 100.00 | |||
| entropy_src_rng | 198.000s | 13091.857us | 1 | 1 | 100.00 | |
| interrupts | 2 | 2 | 100.00 | |||
| entropy_src_rng | 198.000s | 13091.857us | 1 | 1 | 100.00 | |
| entropy_src_intr | 9.000s | 7452.226us | 1 | 1 | 100.00 | |
| alerts | 2 | 2 | 100.00 | |||
| entropy_src_rng | 198.000s | 13091.857us | 1 | 1 | 100.00 | |
| entropy_src_functional_alerts | 4.000s | 1027.381us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| entropy_src_stress_all | 42.000s | 14282.195us | 1 | 1 | 100.00 | |
| functional_errors | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 49.157us | 1 | 1 | 100.00 | |
| firmware_ov_read_contiguous_data | 1 | 1 | 100.00 | |||
| entropy_src_fw_ov_contiguous | 2.000s | 47.192us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| entropy_src_intr_test | 2.000s | 17.062us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| entropy_src_alert_test | 2.000s | 54.998us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 5.000s | 171.766us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 5.000s | 171.766us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 1.000s | 20.389us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 1.000s | 104.785us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 2.000s | 109.122us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 3.000s | 183.816us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 1.000s | 20.389us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 1.000s | 104.785us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 2.000s | 109.122us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 3.000s | 183.816us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| entropy_src_sec_cm | 3.000s | 133.305us | 1 | 1 | 100.00 | |
| entropy_src_tl_intg_err | 2.000s | 104.014us | 1 | 1 | 100.00 | |
| sec_cm_config_regwen | 2 | 2 | 100.00 | |||
| entropy_src_rng | 198.000s | 13091.857us | 1 | 1 | 100.00 | |
| entropy_src_cfg_regwen | 2.000s | 18.434us | 1 | 1 | 100.00 | |
| sec_cm_config_mubi | 1 | 1 | 100.00 | |||
| entropy_src_rng | 198.000s | 13091.857us | 1 | 1 | 100.00 | |
| sec_cm_config_redun | 1 | 1 | 100.00 | |||
| entropy_src_rng | 198.000s | 13091.857us | 1 | 1 | 100.00 | |
| sec_cm_intersig_mubi | 1 | 2 | 50.00 | |||
| entropy_src_rng | 198.000s | 13091.857us | 1 | 1 | 100.00 | |
| entropy_src_fw_ov | 3601.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 49.157us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 133.305us | 1 | 1 | 100.00 | |
| sec_cm_ack_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 49.157us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 133.305us | 1 | 1 | 100.00 | |
| sec_cm_rng_bkgn_chk | 1 | 1 | 100.00 | |||
| entropy_src_rng | 198.000s | 13091.857us | 1 | 1 | 100.00 | |
| sec_cm_fifo_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 49.157us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 133.305us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 49.157us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 133.305us | 1 | 1 | 100.00 | |
| sec_cm_ctr_local_esc | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 49.157us | 1 | 1 | 100.00 | |
| sec_cm_esfinal_rdata_bus_consistency | 1 | 1 | 100.00 | |||
| entropy_src_functional_alerts | 4.000s | 1027.381us | 1 | 1 | 100.00 | |
| sec_cm_tile_link_bus_integrity | 1 | 1 | 100.00 | |||
| entropy_src_tl_intg_err | 2.000s | 104.014us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| external_health_tests | 1 | 1 | 100.00 | |||
| entropy_src_rng_with_xht_rsps | 220.000s | 13094.481us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| entropy_src_stress_all_with_rand_reset | 1.000s | 9.502us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_lo_total_fails | 2 test runs | |||
| entropy_src_stress_all_with_rand_reset | 68151314348528952881314323299803418931660018402758855164621835338148410199751 | 112 |
UVM_INFO @ 9502424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| entropy_src_csr_mem_rw_with_rand_reset | 20756088594006926175637076018121450786425125346172579360697596114705986784101 | 113 |
UVM_INFO @ 9188781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 1 test run | |||
| entropy_src_fw_ov | 71142669085739947402798569465438469819062543342657316627152677678235559876165 | None | ||