Simulation Results: flash_ctrl

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.55 %
  • code
  • 93.81 %
  • assert
  • 97.02 %
  • func
  • 95.82 %
  • line
  • 95.94 %
  • branch
  • 97.14 %
  • cond
  • 93.78 %
  • toggle
  • 95.78 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
98.28%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 59.160s 623.283us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 15.080s 18.405us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 11.140s 36.679us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.800s 152.138us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 32.150s 15357.349us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 46.370s 7185.315us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 13.430s 186.634us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.800s 152.138us 1 1 100.00
flash_ctrl_csr_aliasing 46.370s 7185.315us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.020s 30.190us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.020s 32.033us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.690s 38.580us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 20.920s 63.653us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1119.690s 278162.466us 1 1 100.00
flash_ctrl_hw_rma_reset 504.380s 40128.206us 1 1 100.00
flash_ctrl_lcmgr_intg 6.300s 39.106us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 992.480s 569216.775us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 135.150s 3939.978us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 8.950s 21.487us 1 1 100.00
full_memory_access 0 1 0.00
flash_ctrl_full_mem_access 1315.000s 85247.447us 0 1 0.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 57.910s 1935.540us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 15.430s 33.471us 1 1 100.00
flash_ctrl_rw_evict_all_en 13.280s 35.455us 1 1 100.00
flash_ctrl_re_evict 17.350s 260.620us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 208.170s 6797.323us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 208.170s 6797.323us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 162.840s 26501.816us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 21.610s 816.630us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 464.780s 889.900us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 491.830s 18221.783us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 342.380s 3332.768us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 867.010s 1144.039us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.820s 233.069us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 118.090s 7327.575us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.930s 17.663us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.620s 67.370us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 549.480s 524.779us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 91.920s 16350.633us 1 1 100.00
flash_ctrl_otp_reset 59.220s 410.544us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1119.690s 278162.466us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 109.880s 3384.069us 1 1 100.00
flash_ctrl_intr_wr 54.650s 6763.584us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 168.240s 12624.367us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 122.970s 49476.611us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 43.760s 2407.875us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 39.480s 3176.234us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 10.960s 101.744us 1 1 100.00
flash_ctrl_ro_derr 86.650s 5749.676us 1 1 100.00
flash_ctrl_rw_derr 145.760s 13245.158us 1 1 100.00
flash_ctrl_derr_detect 101.990s 859.896us 1 1 100.00
flash_ctrl_integrity 367.970s 9515.853us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.970s 522.061us 1 1 100.00
flash_ctrl_ro_serr 93.180s 3513.077us 1 1 100.00
flash_ctrl_rw_serr 102.700s 5753.209us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 50.770s 1610.989us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 42.610s 3382.943us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 106.720s 5085.359us 1 1 100.00
flash_ctrl_write_word_sweep 6.790s 162.602us 1 1 100.00
flash_ctrl_read_word_sweep 6.510s 31.014us 1 1 100.00
flash_ctrl_ro 74.370s 8861.652us 1 1 100.00
flash_ctrl_rw 278.330s 15117.850us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 20.760s 1717.064us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 551.690s 47834.804us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 65.370s 10020.891us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.920s 101.494us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.280s 18.923us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 11.320s 133.004us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 11.320s 133.004us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 11.140s 36.679us 1 1 100.00
flash_ctrl_csr_rw 8.800s 152.138us 1 1 100.00
flash_ctrl_csr_aliasing 46.370s 7185.315us 1 1 100.00
flash_ctrl_same_csr_outstanding 16.400s 343.762us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 11.140s 36.679us 1 1 100.00
flash_ctrl_csr_rw 8.800s 152.138us 1 1 100.00
flash_ctrl_csr_aliasing 46.370s 7185.315us 1 1 100.00
flash_ctrl_same_csr_outstanding 16.400s 343.762us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 24.250s 49.677us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 24.250s 49.677us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 24.250s 49.677us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 24.250s 49.677us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 33.040s 984.516us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1654.980s 4880.577us 1 1 100.00
flash_ctrl_tl_intg_err 214.720s 5023.802us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 214.720s 5023.802us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 214.720s 5023.802us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 20.030s 73.561us 1 1 100.00
flash_ctrl_wr_intg 6.710s 49.109us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 59.160s 623.283us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 59.220s 410.544us 1 1 100.00
flash_ctrl_disable 9.930s 17.663us 1 1 100.00
flash_ctrl_sec_info_access 38.160s 1986.651us 1 1 100.00
flash_ctrl_connect 7.620s 67.370us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 10.930s 68.197us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.800s 152.138us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 24.250s 49.677us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.800s 152.138us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 24.250s 49.677us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.800s 152.138us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 24.250s 49.677us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.930s 17.663us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 20.030s 73.561us 1 1 100.00
flash_ctrl_access_after_disable 6.100s 24.226us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 16.570s 32.749us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.930s 17.663us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 21.610s 816.630us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 278.330s 15117.850us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 102.700s 5753.209us 1 1 100.00
flash_ctrl_rw_derr 145.760s 13245.158us 1 1 100.00
flash_ctrl_integrity 367.970s 9515.853us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1119.690s 278162.466us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1654.980s 4880.577us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1654.980s 4880.577us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1654.980s 4880.577us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1654.980s 4880.577us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 13.590s 721.910us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.560s 74.195us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.510s 197.081us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1654.980s 4880.577us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1654.980s 4880.577us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1654.980s 4880.577us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 22.960s 100.058us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 446.190s 4027.270us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (flash_ctrl_scoreboard.sv:735) [scoreboard] Check failed exp_data_part[addr] == data (* [*] vs * [*]) read addr:* data: * 1 test run
flash_ctrl_full_mem_access 30043282296498610150420401458243997310517643827211800962049527787743117819652 275581
UVM_INFO @ 85247446.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---