Simulation Results: hmac

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.46 %
  • code
  • 98.60 %
  • assert
  • 97.16 %
  • func
  • 45.63 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.52 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.060s 681.685us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.890s 230.606us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.940s 46.816us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 12.670s 9369.911us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.130s 632.909us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.930s 19.047us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.940s 46.816us 1 1 100.00
hmac_csr_aliasing 5.130s 632.909us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 34.150s 1259.868us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 33.930s 1219.763us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.050s 223.678us 1 1 100.00
hmac_test_sha384_vectors 348.230s 38943.042us 1 1 100.00
hmac_test_sha512_vectors 20.900s 1338.411us 1 1 100.00
hmac_test_hmac256_vectors 10.380s 1651.377us 1 1 100.00
hmac_test_hmac384_vectors 13.310s 561.185us 1 1 100.00
hmac_test_hmac512_vectors 14.350s 1119.162us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 19.120s 680.168us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 59.180s 1206.913us 1 1 100.00
error 1 1 100.00
hmac_error 71.920s 85553.917us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 55.260s 7063.627us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.060s 681.685us 1 1 100.00
hmac_long_msg 34.150s 1259.868us 1 1 100.00
hmac_back_pressure 33.930s 1219.763us 1 1 100.00
hmac_datapath_stress 59.180s 1206.913us 1 1 100.00
hmac_burst_wr 19.120s 680.168us 1 1 100.00
hmac_stress_all 576.430s 43263.674us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.060s 681.685us 1 1 100.00
hmac_long_msg 34.150s 1259.868us 1 1 100.00
hmac_back_pressure 33.930s 1219.763us 1 1 100.00
hmac_datapath_stress 59.180s 1206.913us 1 1 100.00
hmac_wipe_secret 55.260s 7063.627us 1 1 100.00
hmac_test_sha256_vectors 8.050s 223.678us 1 1 100.00
hmac_test_sha384_vectors 348.230s 38943.042us 1 1 100.00
hmac_test_sha512_vectors 20.900s 1338.411us 1 1 100.00
hmac_test_hmac256_vectors 10.380s 1651.377us 1 1 100.00
hmac_test_hmac384_vectors 13.310s 561.185us 1 1 100.00
hmac_test_hmac512_vectors 14.350s 1119.162us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.060s 681.685us 1 1 100.00
hmac_long_msg 34.150s 1259.868us 1 1 100.00
hmac_back_pressure 33.930s 1219.763us 1 1 100.00
hmac_datapath_stress 59.180s 1206.913us 1 1 100.00
hmac_burst_wr 19.120s 680.168us 1 1 100.00
hmac_error 71.920s 85553.917us 1 1 100.00
hmac_wipe_secret 55.260s 7063.627us 1 1 100.00
hmac_test_sha256_vectors 8.050s 223.678us 1 1 100.00
hmac_test_sha384_vectors 348.230s 38943.042us 1 1 100.00
hmac_test_sha512_vectors 20.900s 1338.411us 1 1 100.00
hmac_test_hmac256_vectors 10.380s 1651.377us 1 1 100.00
hmac_test_hmac384_vectors 13.310s 561.185us 1 1 100.00
hmac_test_hmac512_vectors 14.350s 1119.162us 1 1 100.00
hmac_stress_all 576.430s 43263.674us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 576.430s 43263.674us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.590s 38.139us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.830s 20.906us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.690s 63.437us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.690s 63.437us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.890s 230.606us 1 1 100.00
hmac_csr_rw 0.940s 46.816us 1 1 100.00
hmac_csr_aliasing 5.130s 632.909us 1 1 100.00
hmac_same_csr_outstanding 2.030s 674.680us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.890s 230.606us 1 1 100.00
hmac_csr_rw 0.940s 46.816us 1 1 100.00
hmac_csr_aliasing 5.130s 632.909us 1 1 100.00
hmac_same_csr_outstanding 2.030s 674.680us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.790s 69.900us 1 1 100.00
hmac_tl_intg_err 1.890s 62.595us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.890s 62.595us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.060s 681.685us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.330s 202.208us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 87.210s 34568.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.050s 98.437us 1 1 100.00