Simulation Results

Simulation Results: i2c

18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
84.39 %

code
78.34 %

assert
97.25 %

func
77.59 %

line
96.41 %

branch
92.33 %

cond
85.38 %

toggle
73.52 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	15.610s	11237.775us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	7.170s	1033.108us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.880s	99.717us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.920s	44.506us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.260s	670.590us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.320s	265.314us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.880s	23.013us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.920s	44.506us	1	1	100.00
	i2c_csr_aliasing	1.320s	265.314us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.120s	20.585us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	220.940s	24666.126us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	1.860s	243.932us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.690s	92.908us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	56.780s	15396.563us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	63.220s	19921.786us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.020s	352.378us	1	1	100.00
	i2c_host_fifo_fmt_empty	11.110s	437.599us	1	1	100.00
	i2c_host_fifo_reset_rx	10.100s	991.873us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	30.730s	7980.660us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	14.720s	3461.323us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	1.600s	241.741us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.760s	939.201us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	133.420s	75620.987us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	2.750s	540.222us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	11.750s	1130.638us	1	1	100.00
	i2c_target_intr_smoke	4.150s	1236.018us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.840s	912.049us	1	1	100.00
	i2c_target_fifo_reset_tx	1.400s	189.966us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	350.600s	41647.473us	1	1	100.00
	i2c_target_stress_rd	11.750s	1130.638us	1	1	100.00
	i2c_target_intr_stress_wr	70.370s	9906.590us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.290s	3675.497us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	10.820s	3709.664us	1	1	100.00
bad_address				0	1	0.00
	i2c_target_bad_addr	3.850s	20000.000us	0	1	0.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.510s	4816.016us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.290s	1160.461us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.980s	517.126us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	1.860s	243.932us	1	1	100.00
	i2c_host_perf_precise	595.170s	23234.496us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	14.720s	3461.323us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.390s	349.447us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.750s	498.492us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.080s	1821.819us	1	1	100.00
	i2c_target_nack_txstretch	1.170s	1098.083us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	14.620s	2895.097us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.370s	1766.959us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.870s	41.642us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.950s	26.032us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.360s	456.259us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.360s	456.259us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.880s	99.717us	1	1	100.00
	i2c_csr_rw	0.920s	44.506us	1	1	100.00
	i2c_csr_aliasing	1.320s	265.314us	1	1	100.00
	i2c_same_csr_outstanding	0.960s	66.063us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.880s	99.717us	1	1	100.00
	i2c_csr_rw	0.920s	44.506us	1	1	100.00
	i2c_csr_aliasing	1.320s	265.314us	1	1	100.00
	i2c_same_csr_outstanding	0.960s	66.063us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.230s	58.622us	1	1	100.00
	i2c_sec_cm	0.840s	42.889us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.230s	58.622us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	11.230s	622.596us	1
target_error_intr				1
	i2c_target_unexp_stop	1.150s	211.374us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	7.070s	2483.969us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1296) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	102820411634272554381638592601668799234336754550900709336920199535464433630728	93	UVM_INFO @ 622595864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	18881330798515073354500108913291152005652413805705334413836660939594040348879	92	UVM_INFO @ 2483968537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_host_error_intr	52738226565332936069845413209860901954491515022679016877071767576412626783494	102	UVM_INFO @ 20584602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:714) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_stress_all	91656416538564467332247173832218729731660835266947194248769187599615998413807	129	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @4093864
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	61085313975103257114321730631780003904832110069233152260286446427263510178873	90	UVM_INFO @ 939201325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1382) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	56951440008535453053503552242919320375819561110663627887935474070225217347632	84	UVM_INFO @ 211373682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	i2c_target_bad_addr	74627510072951973826342567157702365288982963260370682183171439466672551844080	84	UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---