Simulation Results: keymgr

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.44 %
  • code
  • 94.50 %
  • assert
  • 97.72 %
  • func
  • 58.09 %
  • line
  • 98.68 %
  • branch
  • 97.63 %
  • cond
  • 93.16 %
  • toggle
  • 97.00 %
  • FSM
  • 86.05 %
Validation stages
V1
100.00%
V2
94.74%
V2S
90.91%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.140s 226.398us 1 1 100.00
random 1 1 100.00
keymgr_random 2.380s 116.726us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.020s 21.227us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.010s 117.336us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 12.310s 5539.924us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 4.870s 138.658us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.070s 118.839us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.010s 117.336us 1 1 100.00
keymgr_csr_aliasing 4.870s 138.658us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 0 1 0.00
keymgr_cfg_regwen 1.020s 7.718us 0 1 0.00
sideload 4 4 100.00
keymgr_sideload 1.760s 272.532us 1 1 100.00
keymgr_sideload_kmac 1.340s 29.043us 1 1 100.00
keymgr_sideload_aes 2.220s 162.043us 1 1 100.00
keymgr_sideload_otbn 1.860s 60.536us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.190s 29.382us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.280s 109.225us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.460s 320.118us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 2.990s 491.078us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 3.740s 182.397us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.790s 123.699us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 12.360s 5103.150us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.760s 10.903us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.720s 28.419us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.470s 61.198us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.470s 61.198us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.020s 21.227us 1 1 100.00
keymgr_csr_rw 1.010s 117.336us 1 1 100.00
keymgr_csr_aliasing 4.870s 138.658us 1 1 100.00
keymgr_same_csr_outstanding 2.220s 229.720us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.020s 21.227us 1 1 100.00
keymgr_csr_rw 1.010s 117.336us 1 1 100.00
keymgr_csr_aliasing 4.870s 138.658us 1 1 100.00
keymgr_same_csr_outstanding 2.220s 229.720us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 4.630s 501.245us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 4.630s 501.245us 1 1 100.00
keymgr_tl_intg_err 3.060s 105.594us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.440s 203.518us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.440s 203.518us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.440s 203.518us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.440s 203.518us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 6.080s 242.077us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 4.630s 501.245us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 4.630s 501.245us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 3.060s 105.594us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.440s 203.518us 1 1 100.00
sec_cm_op_config_regwen 0 1 0.00
keymgr_cfg_regwen 1.020s 7.718us 0 1 0.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 2.380s 116.726us 1 1 100.00
keymgr_csr_rw 1.010s 117.336us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 2.380s 116.726us 1 1 100.00
keymgr_csr_rw 1.010s 117.336us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 2.380s 116.726us 1 1 100.00
keymgr_csr_rw 1.010s 117.336us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.280s 109.225us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.740s 182.397us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.740s 182.397us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 2.380s 116.726us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.200s 314.206us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.630s 501.245us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.630s 501.245us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 4.630s 501.245us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 3.330s 189.050us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.280s 109.225us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 4.630s 501.245us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.630s 501.245us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 4.630s 501.245us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.330s 189.050us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.330s 189.050us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 4.630s 501.245us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.330s 189.050us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.630s 501.245us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 3.330s 189.050us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
keymgr_stress_all_with_rand_reset 3.780s 219.635us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:419) scoreboard [scoreboard] Waited * cycles but did not see alert recov_operation_err. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
keymgr_cfg_regwen 37533141031462501100622161888606219987992313433467941439514607009160582554530 147
UVM_INFO @ 7718263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---