Simulation Results: lc_ctrl/volatile_unlock_disabled

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.97 %
  • code
  • 84.48 %
  • assert
  • 94.69 %
  • func
  • 93.73 %
  • line
  • 97.28 %
  • branch
  • 93.85 %
  • cond
  • 79.86 %
  • toggle
  • 86.93 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.450s 17.424us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.180s 119.623us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.150s 19.301us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.770s 221.268us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.260s 29.566us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.520s 48.500us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.150s 19.301us 1 1 100.00
lc_ctrl_csr_aliasing 1.260s 29.566us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.760s 57.842us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.490s 1124.328us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.840s 13.545us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.960s 76.297us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.130s 730.864us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.250s 331.728us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.130s 730.864us 1 1 100.00
lc_ctrl_prog_failure 1.960s 76.297us 1 1 100.00
lc_ctrl_errors 5.250s 331.728us 1 1 100.00
lc_ctrl_security_escalation 5.440s 1561.246us 1 1 100.00
lc_ctrl_jtag_state_failure 17.360s 1546.836us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.630s 266.508us 1 1 100.00
lc_ctrl_jtag_errors 14.670s 3095.065us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.270s 1300.108us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.850s 2618.616us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.630s 266.508us 1 1 100.00
lc_ctrl_jtag_errors 14.670s 3095.065us 1 1 100.00
lc_ctrl_jtag_access 5.080s 4703.992us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 19.890s 1084.124us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.650s 378.357us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.920s 80.870us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.340s 2604.547us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.700s 1887.430us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.990s 117.539us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.710s 311.888us 1 1 100.00
lc_ctrl_jtag_alert_test 1.080s 39.379us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 9.910s 1539.920us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.820s 24.614us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 52.860s 20128.457us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.240s 27.245us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.030s 44.696us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.030s 44.696us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.180s 119.623us 1 1 100.00
lc_ctrl_csr_rw 1.150s 19.301us 1 1 100.00
lc_ctrl_csr_aliasing 1.260s 29.566us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.100s 31.031us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.180s 119.623us 1 1 100.00
lc_ctrl_csr_rw 1.150s 19.301us 1 1 100.00
lc_ctrl_csr_aliasing 1.260s 29.566us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.100s 31.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.570s 134.071us 1 1 100.00
lc_ctrl_tl_intg_err 1.760s 120.811us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.760s 120.811us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.490s 1124.328us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.130s 730.864us 1 1 100.00
lc_ctrl_sec_cm 5.570s 134.071us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.130s 730.864us 1 1 100.00
lc_ctrl_sec_cm 5.570s 134.071us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.130s 730.864us 1 1 100.00
lc_ctrl_sec_cm 5.570s 134.071us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.130s 730.864us 1 1 100.00
lc_ctrl_sec_cm 5.570s 134.071us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.130s 730.864us 1 1 100.00
lc_ctrl_sec_cm 5.570s 134.071us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.130s 730.864us 1 1 100.00
lc_ctrl_sec_cm 5.570s 134.071us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.130s 730.864us 1 1 100.00
lc_ctrl_sec_cm 5.570s 134.071us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.130s 730.864us 1 1 100.00
lc_ctrl_sec_cm 5.570s 134.071us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.440s 1561.246us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.760s 57.842us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.850s 2618.616us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.130s 2272.304us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.130s 2272.304us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.030s 2289.506us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.910s 248.004us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.910s 248.004us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 17.300s 6288.367us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:933) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 56318313744142440831153951990324989506464994337940599096417143785220903223261 694
UVM_INFO @ 6288367372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---