Simulation Results: lc_ctrl/volatile_unlock_enabled

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.70 %
  • code
  • 83.94 %
  • assert
  • 94.97 %
  • func
  • 93.19 %
  • line
  • 97.17 %
  • branch
  • 93.66 %
  • cond
  • 79.75 %
  • toggle
  • 85.57 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.560s 43.709us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.760s 49.632us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.800s 37.743us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.510s 134.393us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 28.661us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.870s 20.952us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.800s 37.743us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 28.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.930s 70.807us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.140s 1266.975us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.870s 41.008us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.720s 119.874us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.190s 1277.444us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.770s 354.619us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.190s 1277.444us 1 1 100.00
lc_ctrl_prog_failure 1.720s 119.874us 1 1 100.00
lc_ctrl_errors 4.770s 354.619us 1 1 100.00
lc_ctrl_security_escalation 3.830s 219.324us 1 1 100.00
lc_ctrl_jtag_state_failure 24.060s 1969.030us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.170s 1872.492us 1 1 100.00
lc_ctrl_jtag_errors 21.450s 2889.255us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 7.880s 2276.473us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.050s 1376.861us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.170s 1872.492us 1 1 100.00
lc_ctrl_jtag_errors 21.450s 2889.255us 1 1 100.00
lc_ctrl_jtag_access 4.350s 1480.045us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.070s 1025.168us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.320s 850.050us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.110s 321.451us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.770s 1724.367us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.100s 2767.406us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.270s 90.743us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.230s 173.713us 1 1 100.00
lc_ctrl_jtag_alert_test 0.750s 20.744us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.970s 2048.741us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.910s 15.729us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 41.450s 74083.503us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.900s 15.812us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.590s 289.150us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.590s 289.150us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.760s 49.632us 1 1 100.00
lc_ctrl_csr_rw 0.800s 37.743us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 28.661us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.850s 107.054us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.760s 49.632us 1 1 100.00
lc_ctrl_csr_rw 0.800s 37.743us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 28.661us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.850s 107.054us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.280s 439.300us 1 1 100.00
lc_ctrl_tl_intg_err 1.670s 62.294us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.670s 62.294us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.140s 1266.975us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.190s 1277.444us 1 1 100.00
lc_ctrl_sec_cm 6.280s 439.300us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.190s 1277.444us 1 1 100.00
lc_ctrl_sec_cm 6.280s 439.300us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.190s 1277.444us 1 1 100.00
lc_ctrl_sec_cm 6.280s 439.300us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.190s 1277.444us 1 1 100.00
lc_ctrl_sec_cm 6.280s 439.300us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.190s 1277.444us 1 1 100.00
lc_ctrl_sec_cm 6.280s 439.300us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.190s 1277.444us 1 1 100.00
lc_ctrl_sec_cm 6.280s 439.300us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.190s 1277.444us 1 1 100.00
lc_ctrl_sec_cm 6.280s 439.300us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.190s 1277.444us 1 1 100.00
lc_ctrl_sec_cm 6.280s 439.300us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.830s 219.324us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.930s 70.807us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.050s 1376.861us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.760s 308.077us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.760s 308.077us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.380s 297.083us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.620s 234.321us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.620s 234.321us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 24.260s 2273.224us 1 1 100.00