Simulation Results: otbn

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.68 %
  • code
  • 86.20 %
  • assert
  • 90.10 %
  • func
  • 98.73 %
  • block
  • 99.27 %
  • line
  • 99.46 %
  • branch
  • 94.86 %
  • toggle
  • 84.28 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 11.000s 683.147us 1 1 100.00
otbn_smoke_vectorized 6.000s 77.091us 1 1 100.00
single_binary 1 1 100.00
otbn_single 6.000s 25.376us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 63.133us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 16.674us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 8.000s 170.925us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 34.579us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 42.210us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 16.674us 1 1 100.00
otbn_csr_aliasing 4.000s 34.579us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 47.000s 3101.295us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 45.000s 1095.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 21.000s 328.589us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 57.000s 164.556us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 19.000s 622.692us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 72.000s 663.802us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 7.000s 30.294us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 12.000s 54.097us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 9.000s 207.508us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 13.184us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 53.446us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 7.000s 439.680us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 7.000s 439.680us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 63.133us 1 1 100.00
otbn_csr_rw 4.000s 16.674us 1 1 100.00
otbn_csr_aliasing 4.000s 34.579us 1 1 100.00
otbn_same_csr_outstanding 4.000s 18.913us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 63.133us 1 1 100.00
otbn_csr_rw 4.000s 16.674us 1 1 100.00
otbn_csr_aliasing 4.000s 34.579us 1 1 100.00
otbn_same_csr_outstanding 4.000s 18.913us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 9.000s 27.295us 1 1 100.00
otbn_dmem_err 8.000s 28.131us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 13.000s 32.824us 1 1 100.00
otbn_controller_ispr_rdata_err 11.000s 372.127us 1 1 100.00
otbn_mac_bignum_acc_err 8.000s 73.953us 0 1 0.00
otbn_urnd_err 5.000s 23.836us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 26.207us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 10.000s 40.161us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 16.123us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 217.000s 1171.742us 1 1 100.00
otbn_tl_intg_err 18.000s 471.461us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 4.000s 16.313us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 217.000s 1171.742us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 217.000s 1171.742us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 683.147us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 8.000s 28.131us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 9.000s 27.295us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 18.000s 471.461us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 7.000s 30.294us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 27.295us 1 1 100.00
otbn_dmem_err 8.000s 28.131us 1 1 100.00
otbn_zero_state_err_urnd 12.000s 54.097us 1 1 100.00
otbn_illegal_mem_acc 5.000s 26.207us 1 1 100.00
otbn_sec_cm 217.000s 1171.742us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 217.000s 1171.742us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 6.000s 25.376us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 27.295us 1 1 100.00
otbn_dmem_err 8.000s 28.131us 1 1 100.00
otbn_zero_state_err_urnd 12.000s 54.097us 1 1 100.00
otbn_illegal_mem_acc 5.000s 26.207us 1 1 100.00
otbn_sec_cm 217.000s 1171.742us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 217.000s 1171.742us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 7.000s 30.294us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 27.295us 1 1 100.00
otbn_dmem_err 8.000s 28.131us 1 1 100.00
otbn_zero_state_err_urnd 12.000s 54.097us 1 1 100.00
otbn_illegal_mem_acc 5.000s 26.207us 1 1 100.00
otbn_sec_cm 217.000s 1171.742us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 217.000s 1171.742us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 6.000s 25.376us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 7.000s 13.704us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 13.563us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 69.000s 649.167us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 69.000s 649.167us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 10.000s 34.728us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 217.000s 1171.742us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 217.000s 1171.742us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 12.000s 39.684us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 217.000s 1171.742us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 217.000s 1171.742us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 18.000s 187.020us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 18.000s 187.020us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 58.972us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 25.376us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 25.376us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 6.000s 25.376us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 19.000s 622.692us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 6.000s 25.376us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 6.000s 25.376us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 40.000s 173.607us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 6.000s 25.376us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 217.000s 1171.742us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 236.000s 5838.826us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_mac_bignum_acc_err 71695374981449319599826264663113135269942964392035477768491784200310392227802 122
UVM_INFO @ 73952753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 76566394834131845729341871505926667850833307507868372722355862860553938325815 86
UVM_INFO @ 16313052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---