Simulation Results: otp_ctrl

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.07 %
  • code
  • 76.59 %
  • assert
  • 94.13 %
  • func
  • 69.50 %
  • line
  • 88.42 %
  • branch
  • 83.22 %
  • cond
  • 90.18 %
  • toggle
  • 77.88 %
  • FSM
  • 43.23 %
Validation stages
V1
100.00%
V2
95.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.490s 788.784us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 5.820s 446.638us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.720s 387.401us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.680s 141.542us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.050s 2363.665us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.270s 81.347us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.210s 149.528us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.680s 141.542us 1 1 100.00
otp_ctrl_csr_aliasing 3.270s 81.347us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.600s 76.856us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.690s 563.398us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 15.110s 1660.913us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.740s 168.537us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 14.850s 1590.446us 1 1 100.00
otp_ctrl_check_fail 6.850s 903.750us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.260s 726.318us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 18.120s 3475.391us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 13.600s 921.547us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 7.950s 599.422us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.040s 362.581us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 17.190s 1053.465us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 18.480s 9867.778us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 15.990s 1466.954us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 8.260s 363.007us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.100s 577.230us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.780s 68.827us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.650s 126.787us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.650s 126.787us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.720s 387.401us 1 1 100.00
otp_ctrl_csr_rw 1.680s 141.542us 1 1 100.00
otp_ctrl_csr_aliasing 3.270s 81.347us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.120s 174.176us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.720s 387.401us 1 1 100.00
otp_ctrl_csr_rw 1.680s 141.542us 1 1 100.00
otp_ctrl_csr_aliasing 3.270s 81.347us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.120s 174.176us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
otp_ctrl_tl_intg_err 6.590s 903.637us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 6.590s 903.637us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 5.820s 446.638us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 5.820s 446.638us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.040s 362.581us 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.040s 362.581us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.040s 362.581us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.040s 362.581us 1 1 100.00
otp_ctrl_macro_errs 18.480s 9867.778us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.040s 362.581us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.040s 362.581us 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.040s 362.581us 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.040s 362.581us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.040s 362.581us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.040s 362.581us 1 1 100.00
otp_ctrl_macro_errs 18.480s 9867.778us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.040s 362.581us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.040s 362.581us 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.740s 168.537us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 6.850s 903.750us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 18.120s 3475.391us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 18.120s 3475.391us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 18.120s 3475.391us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 18.120s 3475.391us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 18.120s 3475.391us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 5.820s 446.638us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 18.120s 3475.391us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 5.820s 446.638us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 200.120s 179149.101us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.260s 726.318us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 5.820s 446.638us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 5.820s 446.638us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 18.480s 9867.778us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 11.120s 3601.563us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 53.200s 17452.799us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 1245253199420454176152872381814125573348599451141385241271894190691507768084 7306
UVM_INFO @ 903749979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all_with_rand_reset 49960656460047774702969775464642606061519853221421064161347808951262269409994 7312
UVM_INFO @ 17452798652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---