Simulation Results: pwrmgr

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.39 %
  • code
  • 94.54 %
  • assert
  • 97.91 %
  • func
  • 96.71 %
  • line
  • 98.92 %
  • branch
  • 95.61 %
  • cond
  • 94.34 %
  • toggle
  • 89.83 %
  • FSM
  • 94.00 %
Validation stages
V1
83.33%
V2
93.33%
V2S
72.73%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.630s 34.260us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.660s 89.973us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.770s 18.918us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.710s 1355.429us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.870s 48.987us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
pwrmgr_csr_mem_rw_with_rand_reset 3600.021s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.770s 18.918us 1 1 100.00
pwrmgr_csr_aliasing 0.870s 48.987us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.680s 137.563us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.680s 137.563us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.880s 37.380us 1 1 100.00
pwrmgr_lowpower_invalid 0.620s 73.642us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.700s 42.779us 1 1 100.00
pwrmgr_reset_invalid 0.740s 227.238us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.700s 42.779us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.880s 174.511us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.720s 87.655us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.910s 184.500us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 10800.021s 0.000us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.600s 35.700us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.630s 400.489us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.630s 400.489us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.660s 89.973us 1 1 100.00
pwrmgr_csr_rw 0.770s 18.918us 1 1 100.00
pwrmgr_csr_aliasing 0.870s 48.987us 1 1 100.00
pwrmgr_same_csr_outstanding 0.750s 24.798us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.660s 89.973us 1 1 100.00
pwrmgr_csr_rw 0.770s 18.918us 1 1 100.00
pwrmgr_csr_aliasing 0.870s 48.987us 1 1 100.00
pwrmgr_same_csr_outstanding 0.750s 24.798us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 3600.021s 0.000us 0 1 0.00
pwrmgr_sec_cm 3600.031s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 3600.031s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 3600.031s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 3600.021s 0.000us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.930s 825.615us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.880s 174.511us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.800s 954.389us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.810s 101.371us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.590s 40.213us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 3600.031s 0.000us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 3600.031s 0.000us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 3600.031s 0.000us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.730s 48.257us 1 1 100.00
sec_cm_main_pd_rst_local_esc 0 1 0.00
pwrmgr_glitch 3600.023s 0.000us 0 1 0.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.920s 215.802us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.770s 18.918us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.770s 18.918us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.720s 134.279us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 3600.022s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 6 test runs
pwrmgr_glitch 10956645513041243336180027414325977451604080879345728263387019418302722596021 None
pwrmgr_tl_intg_err 102198888211694411044891641844931663146742059466681399286424108734440142120485 None
pwrmgr_sec_cm 37545988158051011191072864182547515909055341297864586520472245633663389290490 None
pwrmgr_stress_all_with_rand_reset 76341667004419812335905952518237897627441608623118436771384886915144224540833 None
pwrmgr_stress_all 98963511257705517178389633596167925525391960433021899197620135204855854717800 None
pwrmgr_csr_mem_rw_with_rand_reset 21234038175138750953582882831025680240232629604827899582773868620915199442855 None