Simulation Results: rom_ctrl/32kb

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.64 %
  • code
  • 92.52 %
  • assert
  • 96.81 %
  • func
  • 97.59 %
  • line
  • 98.81 %
  • branch
  • 97.81 %
  • cond
  • 97.47 %
  • toggle
  • 95.19 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 2.890s 803.665us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 2.620s 241.329us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 1.930s 49.298us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.770s 88.208us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 1.780s 69.793us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.040s 103.835us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 1.930s 49.298us 1 1 100.00
rom_ctrl_csr_aliasing 1.780s 69.793us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 1.800s 102.650us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 1.700s 136.841us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.450s 164.063us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 7.470s 1131.831us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 3.130s 55.752us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 1.670s 84.006us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 3.380s 75.546us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 3.380s 75.546us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 2.620s 241.329us 1 1 100.00
rom_ctrl_csr_rw 1.930s 49.298us 1 1 100.00
rom_ctrl_csr_aliasing 1.780s 69.793us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.780s 520.960us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 2.620s 241.329us 1 1 100.00
rom_ctrl_csr_rw 1.930s 49.298us 1 1 100.00
rom_ctrl_csr_aliasing 1.780s 69.793us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.780s 520.960us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.830s 10352.126us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 12.560s 2011.929us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 191.160s 1400.469us 1 1 100.00
rom_ctrl_tl_intg_err 43.840s 360.306us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 191.160s 1400.469us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 191.160s 1400.469us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.830s 10352.126us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.830s 10352.126us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.830s 10352.126us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.830s 10352.126us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.830s 10352.126us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 191.160s 1400.469us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 191.160s 1400.469us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 2.890s 803.665us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 2.890s 803.665us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 2.890s 803.665us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 43.840s 360.306us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.830s 10352.126us 1 1 100.00
rom_ctrl_kmac_err_chk 3.130s 55.752us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.830s 10352.126us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.830s 10352.126us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.830s 10352.126us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 12.560s 2011.929us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 191.160s 1400.469us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 92.290s 1851.841us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 22669976359035878976742614176527526381861805598774249844050087180332789294417 85
UVM_INFO @ 164062764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---