Simulation Results: rstmgr

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.80 %
  • code
  • 99.32 %
  • assert
  • 98.80 %
  • func
  • 95.27 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.68 %
  • toggle
  • 99.25 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.770s 276.997us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.940s 125.325us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.920s 86.404us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 5.620s 1449.674us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.780s 410.201us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.300s 198.242us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.920s 86.404us 1 1 100.00
rstmgr_csr_aliasing 2.780s 410.201us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.160s 181.856us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.870s 437.122us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.010s 149.660us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.000s 1779.303us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.000s 1779.303us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.000s 1779.303us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.000s 1779.303us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 1.530s 449.611us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.070s 65.286us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.420s 303.039us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.420s 303.039us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.940s 125.325us 1 1 100.00
rstmgr_csr_rw 0.920s 86.404us 1 1 100.00
rstmgr_csr_aliasing 2.780s 410.201us 1 1 100.00
rstmgr_same_csr_outstanding 1.400s 108.665us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.940s 125.325us 1 1 100.00
rstmgr_csr_rw 0.920s 86.404us 1 1 100.00
rstmgr_csr_aliasing 2.780s 410.201us 1 1 100.00
rstmgr_same_csr_outstanding 1.400s 108.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 18.670s 16995.453us 1 1 100.00
rstmgr_tl_intg_err 2.260s 809.003us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 18.670s 16995.453us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 18.670s 16995.453us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.260s 809.003us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.170s 123.367us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 7.220s 2808.932us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.380s 302.536us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 18.670s 16995.453us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.920s 86.404us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.920s 86.404us 1 1 100.00