Simulation Results: rv_timer

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.79 %
  • code
  • 94.66 %
  • assert
  • 96.82 %
  • func
  • 95.88 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.710s 127.313us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.650s 57.624us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.570s 16.255us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.370s 195.241us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.910s 149.497us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.760s 20.090us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.570s 16.255us 1 1 100.00
rv_timer_csr_aliasing 0.910s 149.497us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.840s 179.458us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 1.700s 1004.038us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 243.730s 264032.104us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 243.730s 264032.104us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.250s 936.478us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.610s 45.048us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.630s 13.348us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.830s 294.799us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.830s 294.799us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.650s 57.624us 1 1 100.00
rv_timer_csr_rw 0.570s 16.255us 1 1 100.00
rv_timer_csr_aliasing 0.910s 149.497us 1 1 100.00
rv_timer_same_csr_outstanding 0.640s 15.690us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.650s 57.624us 1 1 100.00
rv_timer_csr_rw 0.570s 16.255us 1 1 100.00
rv_timer_csr_aliasing 0.910s 149.497us 1 1 100.00
rv_timer_same_csr_outstanding 0.640s 15.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.860s 359.296us 1 1 100.00
rv_timer_tl_intg_err 1.050s 80.254us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.050s 80.254us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.540s 36.633us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.590s 90.174us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 21.190s 3570.904us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 65948164122044332931313661451941091510958671124211056875706998769797463370239 82
UVM_INFO @ 90173893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---