Simulation Results: spi_host

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.60 %
  • code
  • 91.30 %
  • assert
  • 95.27 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 19.000s 5455.683us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 35.276us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 117.380us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 499.008us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 28.493us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 37.036us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 117.380us 1 1 100.00
spi_host_csr_aliasing 1.000s 28.493us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 31.363us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 17.853us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 25.980us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 7.000s 25.842us 1 1 100.00
spi_host_error_cmd 1.000s 22.188us 1 1 100.00
spi_host_event 34.000s 10690.752us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 34.330us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 34.330us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 34.330us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 14.000s 646.220us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 83.349us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 73.664us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 34.330us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 34.330us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 19.000s 5455.683us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 19.000s 5455.683us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 94.840us 1 1 100.00
spien 1 1 100.00
spi_host_spien 7.000s 6138.454us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 38.000s 15076.199us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 60.401us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 7.000s 25.842us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 25.445us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 90.130us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 1.000s 191.618us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 1.000s 191.618us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 35.276us 1 1 100.00
spi_host_csr_rw 1.000s 117.380us 1 1 100.00
spi_host_csr_aliasing 1.000s 28.493us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 112.012us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 35.276us 1 1 100.00
spi_host_csr_rw 1.000s 117.380us 1 1 100.00
spi_host_csr_aliasing 1.000s 28.493us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 112.012us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 101.172us 1 1 100.00
spi_host_sec_cm 2.000s 142.728us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 101.172us 1 1 100.00