Simulation Results: sram_ctrl/main

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.81 %
  • code
  • 95.09 %
  • assert
  • 97.96 %
  • func
  • 94.37 %
  • block
  • 94.48 %
  • line
  • 95.64 %
  • branch
  • 92.86 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 6.000s 707.141us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 19.659us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 51.393us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 463.011us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.840us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 728.210us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 51.393us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.840us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 218.000s 26599.189us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 56.000s 11587.188us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 6.000s 2047.586us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 149.000s 22500.325us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 158.000s 69998.732us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 35.000s 9545.628us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 16.000s 41826.321us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 9.000s 4170.893us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 7.000s 1924.872us 1 1 100.00
sram_ctrl_partial_access_b2b 214.000s 66837.849us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 695.969us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 2779.599us 1 1 100.00
sram_ctrl_throughput_w_readback 3.000s 1320.579us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 15.000s 11572.027us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 355.765us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 269.000s 658239.581us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 28.016us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 154.089us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 154.089us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 19.659us 1 1 100.00
sram_ctrl_csr_rw 2.000s 51.393us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.840us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 36.717us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 19.659us 1 1 100.00
sram_ctrl_csr_rw 2.000s 51.393us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.840us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 36.717us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.000s 14207.765us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 783.195us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 338.770us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 783.195us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 338.770us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 15.000s 11572.027us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 15.000s 11572.027us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 51.393us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 9.000s 4170.893us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 4170.893us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 4170.893us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 16.000s 41826.321us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.000s 14207.765us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 707.141us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 707.141us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 9.000s 4170.893us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 783.195us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 16.000s 41826.321us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 783.195us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 783.195us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 6.000s 707.141us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 783.195us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 12.000s 3812.515us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 9222601657181031469695281464665741048855693376810360093629302157423543120423 None
sram_ctrl_mubi_enc_err 102422271603734304559387993132526115505536213199812858995549849730439938729196 None