Simulation Results: sram_ctrl/ret

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.45 %
  • code
  • 81.75 %
  • assert
  • 97.81 %
  • func
  • 94.80 %
  • block
  • 92.19 %
  • line
  • 93.78 %
  • branch
  • 88.23 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 44.578us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 13.711us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 23.321us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 431.639us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 33.992us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 43.014us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 23.321us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 33.992us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.000s 199.493us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 349.157us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 6.000s 1115.380us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 141.000s 16381.951us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 7.000s 2407.394us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 18.000s 2776.253us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.000s 588.432us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 8.000s 6123.536us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 95.604us 1 1 100.00
sram_ctrl_partial_access_b2b 188.000s 17859.013us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 39.910us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 44.524us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 45.536us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 882.546us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 32.279us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 31.000s 4432.968us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 17.974us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 122.593us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 122.593us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 13.711us 1 1 100.00
sram_ctrl_csr_rw 2.000s 23.321us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 33.992us 1 1 100.00
sram_ctrl_same_csr_outstanding 6.000s 57.339us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 13.711us 1 1 100.00
sram_ctrl_csr_rw 2.000s 23.321us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 33.992us 1 1 100.00
sram_ctrl_same_csr_outstanding 6.000s 57.339us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 221.721us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 8.000s 796.859us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 279.767us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 8.000s 796.859us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 279.767us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 882.546us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 882.546us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 23.321us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 8.000s 6123.536us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 6123.536us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 6123.536us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.000s 588.432us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 221.721us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 44.578us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 44.578us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 8.000s 6123.536us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 8.000s 796.859us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.000s 588.432us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 8.000s 796.859us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 8.000s 796.859us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 44.578us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 8.000s 796.859us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 10.000s 1010.782us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 6993761701332706665701362878329937209450851843405269454112523974466897528548 None
sram_ctrl_mubi_enc_err 49456027136605394859105972576974966679121005703642512499434441098302819133277 None