Simulation Results: sysrst_ctrl

 
18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.71 %
  • code
  • 88.59 %
  • assert
  • 87.55 %
  • func
  • 66.00 %
  • line
  • 94.96 %
  • branch
  • 95.85 %
  • cond
  • 92.52 %
  • toggle
  • 100.00 %
  • FSM
  • 59.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.880s 2113.799us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.460s 2478.730us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.510s 2256.122us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.550s 2291.198us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 4.020s 4049.807us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.590s 2047.186us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 63.910s 35967.298us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 3.320s 2690.160us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.730s 2219.339us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.590s 2047.186us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.320s 2690.160us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 29.970s 200904.954us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 273.720s 156195.583us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 6.660s 3657.665us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.790s 3195.496us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 4.630s 2510.983us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.330s 2131.520us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 5.710s 2933.595us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.790s 2612.337us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 6.470s 75832.493us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 57.520s 36550.583us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 4.110s 8765.488us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.940s 2030.819us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.690s 2014.957us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 4.840s 2055.780us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 4.840s 2055.780us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 4.020s 4049.807us 1 1 100.00
sysrst_ctrl_csr_rw 4.590s 2047.186us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.320s 2690.160us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.140s 5037.713us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 4.020s 4049.807us 1 1 100.00
sysrst_ctrl_csr_rw 4.590s 2047.186us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.320s 2690.160us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.140s 5037.713us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 68.140s 42007.772us 1 1 100.00
sysrst_ctrl_tl_intg_err 21.110s 22314.216us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 21.110s 22314.216us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 9.860s 21032.909us 1 1 100.00