Simulation Results

Simulation Results: uart

18/08/2026 15:30:28 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
82.90 %

code
92.23 %

assert
98.27 %

func
58.21 %

line
99.48 %

branch
98.14 %

cond
96.62 %

toggle
74.67 %

Validation stages

V1		100.00%
V2		95.45%
V2S		100.00%
V3		0.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	24.170s	11037.075us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.650s	13.539us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	0.590s	47.329us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	1.960s	281.505us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	1.010s	36.002us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	0.930s	36.560us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	0.590s	47.329us	1	1	100.00
	uart_csr_aliasing	1.010s	36.002us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	3.610s	29749.121us	1	1	100.00
parity				2	2	100.00
	uart_smoke	24.170s	11037.075us	1	1	100.00
	uart_tx_rx	3.610s	29749.121us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	13.150s	37327.482us	1	1	100.00
	uart_rx_parity_err	28.950s	33769.148us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	3.610s	29749.121us	1	1	100.00
	uart_intr	13.150s	37327.482us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	47.320s	36901.011us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	9.220s	41576.129us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	27.290s	50914.167us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	13.150s	37327.482us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	13.150s	37327.482us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	13.150s	37327.482us	1	1	100.00
perf				1	1	100.00
	uart_perf	45.080s	7455.002us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	15.070s	10587.357us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	15.070s	10587.357us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	11.710s	18248.698us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	3.900s	3614.065us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	7.520s	6586.320us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	3.540s	2352.364us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	386.620s	168927.868us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	139.470s	106947.229us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	0.840s	94.577us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	0.750s	14.976us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	2.710s	275.279us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	2.710s	275.279us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	0.650s	13.539us	1	1	100.00
	uart_csr_rw	0.590s	47.329us	1	1	100.00
	uart_csr_aliasing	1.010s	36.002us	1	1	100.00
	uart_same_csr_outstanding	0.800s	49.676us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	0.650s	13.539us	1	1	100.00
	uart_csr_rw	0.590s	47.329us	1	1	100.00
	uart_csr_aliasing	1.010s	36.002us	1	1	100.00
	uart_same_csr_outstanding	0.800s	49.676us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	1.090s	136.880us	1	1	100.00
	uart_tl_intg_err	1.710s	336.902us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	1.710s	336.902us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	uart_stress_all_with_rand_reset	21.720s	3762.471us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:390) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				1 test run
	uart_noise_filter	88193104717045794579547054014319246658234886479618229322636502647769926263965	83	UVM_ERROR @ 5990334263 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 7909991703 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 7909991703 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 8957869803 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR (cip_base_vseq.sv:1296) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	uart_stress_all_with_rand_reset	5345126705587205064131694083267070358245238259043290679515174194015997157607	131	UVM_ERROR @ 1977735064 ps: (cip_base_vseq.sv:1209) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. UVM_INFO @ 1977735064 ps: (cip_base_vseq.sv:1213) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Issuing reset for run 5/10 UVM_INFO @ 1977750735 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2