Simulation Results: adc_ctrl

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.96 %
  • code
  • 97.35 %
  • assert
  • 96.92 %
  • func
  • 18.61 %
  • line
  • 99.05 %
  • branch
  • 98.51 %
  • cond
  • 94.62 %
  • toggle
  • 100.00 %
  • FSM
  • 94.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 10.020s 5818.384us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.650s 1266.154us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.230s 571.661us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 40.320s 11161.934us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 5.640s 931.128us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.370s 481.038us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.230s 571.661us 1 1 100.00
adc_ctrl_csr_aliasing 5.640s 931.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 36.660s 55305.627us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 13.650s 19173.511us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 55.000s 33690.959us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 35.170s 17708.266us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 85.200s 75332.792us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 86.570s 49589.732us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 70.880s 27090.678us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 89.150s 54872.440us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 11.590s 4281.544us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 93.700s 43211.884us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 145.000s 134169.270us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 26.740s 46523.155us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.770s 480.741us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.310s 453.598us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.540s 815.923us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.540s 815.923us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.650s 1266.154us 1 1 100.00
adc_ctrl_csr_rw 1.230s 571.661us 1 1 100.00
adc_ctrl_csr_aliasing 5.640s 931.128us 1 1 100.00
adc_ctrl_same_csr_outstanding 9.500s 4113.835us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.650s 1266.154us 1 1 100.00
adc_ctrl_csr_rw 1.230s 571.661us 1 1 100.00
adc_ctrl_csr_aliasing 5.640s 931.128us 1 1 100.00
adc_ctrl_same_csr_outstanding 9.500s 4113.835us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 14.630s 7976.571us 1 1 100.00
adc_ctrl_tl_intg_err 9.810s 4378.307us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 9.810s 4378.307us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 19.290s 6402.881us 1 1 100.00