Simulation Results: alert_handler

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.60 %
  • code
  • 91.23 %
  • assert
  • 98.27 %
  • func
  • 76.31 %
  • line
  • 99.78 %
  • branch
  • 97.87 %
  • cond
  • 90.17 %
  • toggle
  • 86.08 %
  • FSM
  • 82.26 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 46.800s 1019.372us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 5.980s 167.552us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.660s 71.230us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 238.670s 10240.550us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 112.570s 3839.956us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 8.820s 155.657us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.660s 71.230us 1 1 100.00
alert_handler_csr_aliasing 112.570s 3839.956us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 92.750s 2371.734us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 5.220s 657.138us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 989.060s 12100.574us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 85.230s 6026.789us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 46.800s 1019.372us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 96.370s 11864.734us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 31.020s 1033.344us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 29.900s 696.648us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 3495.700s 319000.397us 1 1 100.00
alert_handler_lpg_stub_clk 1390.410s 116589.961us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 3100.140s 72154.976us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 13.950s 669.513us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.580s 36.820us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 2.010s 29.301us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 18.030s 2927.566us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 18.030s 2927.566us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 5.980s 167.552us 1 1 100.00
alert_handler_csr_rw 4.660s 71.230us 1 1 100.00
alert_handler_csr_aliasing 112.570s 3839.956us 1 1 100.00
alert_handler_same_csr_outstanding 26.070s 770.481us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 5.980s 167.552us 1 1 100.00
alert_handler_csr_rw 4.660s 71.230us 1 1 100.00
alert_handler_csr_aliasing 112.570s 3839.956us 1 1 100.00
alert_handler_same_csr_outstanding 26.070s 770.481us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 132.670s 7981.218us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 132.670s 7981.218us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 132.670s 7981.218us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 132.670s 7981.218us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 271.660s 12627.972us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 32.940s 969.699us 1 1 100.00
alert_handler_tl_intg_err 5.210s 184.011us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 5.210s 184.011us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 132.670s 7981.218us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 46.800s 1019.372us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 46.800s 1019.372us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 46.800s 1019.372us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 46.800s 1019.372us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 85.230s 6026.789us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 3495.700s 319000.397us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 85.230s 6026.789us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 989.060s 12100.574us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 989.060s 12100.574us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 32.940s 969.699us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 32.940s 969.699us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 32.940s 969.699us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 32.940s 969.699us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 32.940s 969.699us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 32.940s 969.699us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 32.940s 969.699us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 32.940s 969.699us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 32.940s 969.699us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 136.680s 1487.136us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:482) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 59398183578699450228671752392942167443685516112493078102486457437050319770039 90
UVM_INFO @ 696647619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 23578092887395252531160243696744348200931742855747843409006411710856540526677 208
UVM_INFO @ 669513084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 101743737227425657624465257064638580956410296388670733049385252471107968380238 200
UVM_INFO @ 1487135946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---