Simulation Results: chip

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.30 %
  • code
  • 81.09 %
  • assert
  • 97.49 %
  • func
  • 56.32 %
  • line
  • 94.15 %
  • branch
  • 93.60 %
  • cond
  • 88.38 %
  • toggle
  • 72.19 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
74.28%
V2S
100.00%
V3
56.00%
unmapped
36.36%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 243.640s 3295.964us 1 1 100.00
chip_sw_example_rom 190.420s 3169.634us 1 1 100.00
chip_sw_example_manufacturer 239.260s 3168.211us 1 1 100.00
chip_sw_example_concurrency 238.590s 3279.011us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 552.500s 10445.783us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 396.090s 7215.093us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 569.010s 7102.154us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4001.620s 30965.867us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 273.260s 4382.430us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4001.620s 30965.867us 1 1 100.00
chip_csr_rw 396.090s 7215.093us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 5.760s 41.642us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 456.350s 4827.264us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 456.350s 4827.264us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 456.350s 4827.264us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 537.930s 4303.305us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 537.930s 4303.305us 1 1 100.00
chip_sw_uart_tx_rx_idx1 527.690s 4611.355us 1 1 100.00
chip_sw_uart_tx_rx_idx2 588.020s 5532.316us 1 1 100.00
chip_sw_uart_tx_rx_idx3 557.050s 4661.159us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1373.870s 9410.300us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1386.640s 8484.206us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1269.130s 14145.232us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 377.290s 8131.826us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 377.290s 8131.826us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 337.420s 3634.003us 1 1 100.00
chip_sw_sleep_pin_wake 0 1 0.00
chip_sw_sleep_pin_wake 346.140s 4370.427us 0 1 0.00
chip_sw_sleep_pin_retention 0 1 0.00
chip_sw_sleep_pin_retention 278.680s 3692.573us 0 1 0.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 181.750s 2458.982us 1 1 100.00
chip_tap_straps_testunlock0 310.650s 4486.416us 1 1 100.00
chip_tap_straps_rma 188.180s 3105.167us 1 1 100.00
chip_tap_straps_prod 206.870s 2816.279us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 784.960s 7730.631us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 784.960s 7730.631us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 830.790s 8158.998us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1002.860s 10915.253us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 483.560s 3891.712us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 760.550s 6266.927us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4370.250s 20257.800us 1 1 100.00
chip_sw_aes_enc_jitter_en 283.050s 3524.272us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 860.100s 7679.529us 1 1 100.00
chip_sw_hmac_enc_jitter_en 271.540s 3684.812us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 951.370s 7937.281us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 358.220s 4189.708us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 685.340s 7255.825us 1 1 100.00
chip_sw_clkmgr_jitter 233.990s 2873.093us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 351.900s 4180.844us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 1 2 50.00
chip_sw_sensor_ctrl_alert 983.530s 8370.356us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 242.600s 3143.827us 0 1 0.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 318.410s 3588.190us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 0 1 0.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 242.600s 3143.827us 0 1 0.00
chip_sw_smoketest 16 16 100.00
chip_sw_aes_smoketest 277.850s 3553.892us 1 1 100.00
chip_sw_aon_timer_smoketest 298.990s 3995.780us 1 1 100.00
chip_sw_clkmgr_smoketest 296.340s 4034.769us 1 1 100.00
chip_sw_csrng_smoketest 300.980s 3720.938us 1 1 100.00
chip_sw_entropy_src_smoketest 1120.410s 8224.942us 1 1 100.00
chip_sw_gpio_smoketest 328.790s 3913.689us 1 1 100.00
chip_sw_hmac_smoketest 282.640s 3527.311us 1 1 100.00
chip_sw_kmac_smoketest 331.520s 3756.046us 1 1 100.00
chip_sw_otbn_smoketest 1107.240s 7372.325us 1 1 100.00
chip_sw_pwrmgr_smoketest 519.350s 7564.901us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 529.100s 6437.720us 1 1 100.00
chip_sw_rv_plic_smoketest 244.000s 2930.510us 1 1 100.00
chip_sw_rv_timer_smoketest 242.070s 4117.490us 1 1 100.00
chip_sw_rstmgr_smoketest 266.670s 3542.870us 1 1 100.00
chip_sw_sram_ctrl_smoketest 237.980s 3666.367us 1 1 100.00
chip_sw_uart_smoketest 247.190s 3877.275us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 307.380s 3146.581us 1 1 100.00
chip_sw_rom_functests 1 1 100.00
rom_keymgr_dpe_functest 533.240s 5300.065us 1 1 100.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 19716.140s 129721.136us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3701.430s 16046.287us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 84.580s 10.120us 0 1 0.00
chip_sw_power_idle_load 1 1 100.00
chip_sw_power_idle_load 533.550s 4987.525us 1 1 100.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 287.980s 4913.906us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 688.610s 7353.526us 0 1 0.00
chip_sw_inject_scramble_seed 0 1 0.00
chip_sw_inject_scramble_seed 361.020s 4316.314us 0 1 0.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 99.530s 3035.899us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 99.530s 3035.899us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4001.620s 30965.867us 1 1 100.00
chip_same_csr_outstanding 2653.300s 28032.431us 1 1 100.00
chip_csr_hw_reset 552.500s 10445.783us 1 1 100.00
chip_csr_rw 396.090s 7215.093us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4001.620s 30965.867us 1 1 100.00
chip_same_csr_outstanding 2653.300s 28032.431us 1 1 100.00
chip_csr_hw_reset 552.500s 10445.783us 1 1 100.00
chip_csr_rw 396.090s 7215.093us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 41.220s 466.031us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.480s 45.725us 1 1 100.00
xbar_smoke_large_delays 48.780s 7474.717us 1 1 100.00
xbar_smoke_slow_rsp 42.020s 3810.616us 1 1 100.00
xbar_random_zero_delays 22.300s 338.797us 1 1 100.00
xbar_random_large_delays 37.540s 5389.319us 1 1 100.00
xbar_random_slow_rsp 162.160s 15532.352us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 4.770s 21.796us 1 1 100.00
xbar_error_and_unmapped_addr 27.100s 281.223us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 44.150s 1448.429us 1 1 100.00
xbar_error_and_unmapped_addr 27.100s 281.223us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 40.860s 570.937us 1 1 100.00
xbar_access_same_device_slow_rsp 348.760s 33643.063us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 30.000s 453.157us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 426.440s 14934.634us 1 1 100.00
xbar_stress_all_with_error 310.750s 11099.071us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 240.090s 1769.625us 1 1 100.00
xbar_stress_all_with_reset_error 140.450s 631.630us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3701.430s 16046.287us 1 1 100.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 85.130s 10.340us 0 1 0.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 4026.800s 20811.113us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 84.270s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 85.480s 10.100us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 78.810s 10.400us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 80.880s 10.180us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 82.620s 10.180us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 98.880s 10.100us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 93.460s 10.400us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 88.350s 10.320us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 95.160s 10.120us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 90.850s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 92.790s 10.380us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 82.130s 10.400us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 81.860s 10.180us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 89.040s 10.220us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 83.860s 10.240us 0 1 0.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 3089.720s 12854.107us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 3682.610s 17400.346us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 3828.350s 20181.210us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 3518.650s 16300.635us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 3612.150s 19050.443us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 3162.890s 19002.402us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 3662.740s 17085.516us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 3840.030s 16487.227us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 3962.390s 21776.503us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 3733.220s 18425.392us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 3114.590s 11124.073us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 3955.810s 16323.413us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 3833.570s 17269.950us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 3806.580s 15598.619us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 3696.340s 20023.531us 1 1 100.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 87.560s 10.320us 0 1 0.00
rom_e2e_asm_init_dev 82.720s 10.300us 0 1 0.00
rom_e2e_asm_init_prod 100.860s 10.260us 0 1 0.00
rom_e2e_asm_init_prod_end 94.730s 10.160us 0 1 0.00
rom_e2e_asm_init_rma 85.840s 10.220us 0 1 0.00
rom_e2e_keymgr_dpe_init 3 3 100.00
rom_e2e_keymgr_dpe_init_rom_ext_meas 7553.250s 30909.111us 1 1 100.00
rom_e2e_keymgr_dpe_init_rom_ext_no_meas 7683.910s 34166.991us 1 1 100.00
rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas 7449.970s 33414.085us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3837.280s 16531.741us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3499.910s 34933.861us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3499.910s 34933.861us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 286.360s 3265.950us 1 1 100.00
chip_sw_aes_enc_jitter_en 283.050s 3524.272us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 301.800s 3544.726us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 237.590s 2968.945us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_dpe_sideload_aes 2259.600s 15106.402us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 295.870s 3034.292us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 517.450s 6877.839us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 558.570s 5817.409us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 655.150s 5511.018us 1 1 100.00
chip_plic_all_irqs_10 338.640s 3913.380us 1 1 100.00
chip_plic_all_irqs_20 470.850s 4448.864us 1 1 100.00
chip_sw_alert_handler_entropy 0 1 0.00
chip_sw_alert_handler_entropy 323.490s 2999.308us 0 1 0.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1613.720s 15049.293us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 368.700s 4629.616us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 299.320s 4203.699us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 338.270s 3812.650us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1620.770s 9290.112us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1288.480s 8030.889us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 1022.240s 8175.815us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 10714.930s 255448.766us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 376.620s 4104.977us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 519.350s 7564.901us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 376.620s 4104.977us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 533.720s 9922.748us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 533.720s 9922.748us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 471.200s 8953.371us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 626.030s 6379.963us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 773.530s 6735.299us 1 1 100.00
chip_sw_aes_idle 237.590s 2968.945us 1 1 100.00
chip_sw_hmac_enc_idle 309.530s 3944.691us 1 1 100.00
chip_sw_kmac_idle 283.620s 3995.953us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 544.130s 5141.627us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 489.110s 5838.550us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 376.740s 5203.107us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 395.640s 4506.546us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 1163.890s 13752.837us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 552.510s 4701.253us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 518.800s 5414.487us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 601.320s 5181.489us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 548.930s 5700.358us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 612.200s 4910.680us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 563.210s 5516.108us 1 1 100.00
chip_sw_ast_clk_outputs 830.790s 8158.998us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1682.870s 23599.614us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 601.320s 5181.489us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 548.930s 5700.358us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 483.560s 3891.712us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 760.550s 6266.927us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4370.250s 20257.800us 1 1 100.00
chip_sw_aes_enc_jitter_en 283.050s 3524.272us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 860.100s 7679.529us 1 1 100.00
chip_sw_hmac_enc_jitter_en 271.540s 3684.812us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 951.370s 7937.281us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 358.220s 4189.708us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 685.340s 7255.825us 1 1 100.00
chip_sw_clkmgr_jitter 233.990s 2873.093us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 273.750s 4053.308us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 547.410s 6292.843us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 779.340s 7817.008us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4680.440s 25815.180us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 289.630s 3460.242us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 273.350s 3797.153us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq 1130.080s 12084.375us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 377.880s 4455.404us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 679.190s 7454.339us 1 1 100.00
chip_sw_flash_init_reduced_freq 1817.910s 27953.845us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 5229.100s 33559.895us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 830.790s 8158.998us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 0 1 0.00
chip_sw_clkmgr_sleep_frequency 484.040s 5278.720us 0 1 0.00
chip_sw_clkmgr_reset_frequency 0 1 0.00
chip_sw_clkmgr_reset_frequency 518.900s 6325.080us 0 1 0.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 558.570s 5817.409us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1620.770s 9290.112us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1191.350s 8566.805us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 526.680s 5913.345us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 0 1 0.00
chip_sw_csrng_lc_hw_debug_en_test 310.390s 4527.874us 0 1 0.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 278.450s 3369.723us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2097.590s 10694.277us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 309.320s 3095.083us 1 1 100.00
chip_sw_edn_entropy_reqs 906.440s 8654.174us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 309.320s 3095.083us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1191.350s 8566.805us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 284.270s 3074.956us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1785.520s 27359.920us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 742.700s 5391.554us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 760.550s 6266.927us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 567.660s 4808.501us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 483.560s 3891.712us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 8854.290s 97504.739us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1785.520s 27359.920us 1 1 100.00
chip_sw_flash_idle_low_power 0 1 0.00
chip_sw_flash_ctrl_idle_low_power 436.090s 7274.755us 0 1 0.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 2127.000s 13290.149us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 248.620s 3571.825us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 8854.290s 97504.739us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 248.620s 3571.825us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 248.620s 3571.825us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 248.620s 3571.825us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 248.620s 3571.825us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 558.570s 5817.409us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 338.720s 8671.864us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 799.880s 5660.701us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 553.460s 5807.970us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 553.460s 5807.970us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 351.180s 3654.742us 1 1 100.00
chip_sw_hmac_enc_jitter_en 271.540s 3684.812us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 309.530s 3944.691us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1227.710s 9284.660us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1713.780s 12026.624us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 522.790s 5724.807us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 568.920s 4715.457us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 627.470s 5889.275us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 447.690s 5203.626us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 2 2 100.00
chip_sw_keymgr_dpe_key_derivation 2127.000s 13290.149us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 951.370s 7937.281us 1 1 100.00
chip_sw_keymgr_dpe_sideload_kmac 1 1 100.00
chip_sw_keymgr_dpe_sideload_kmac 1709.910s 12875.448us 1 1 100.00
chip_sw_keymgr_dpe_sideload_aes 1 1 100.00
chip_sw_keymgr_dpe_sideload_aes 2259.600s 15106.402us 1 1 100.00
chip_sw_keymgr_dpe_sideload_otbn 0 1 0.00
chip_sw_keymgr_dpe_sideload_otbn 3600.167s 0.000us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 261.440s 3270.612us 1 1 100.00
chip_sw_kmac_mode_kmac 307.760s 4395.711us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 358.220s 4189.708us 1 1 100.00
chip_sw_kmac_app_keymgr_dpe 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 2127.000s 13290.149us 1 1 100.00
chip_sw_kmac_app_lc 0 1 0.00
chip_sw_lc_ctrl_transition 1092.460s 26608.437us 0 1 0.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 297.130s 3237.422us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1206.140s 7500.688us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 283.620s 3995.953us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 517.450s 6877.839us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 181.750s 2458.982us 1 1 100.00
chip_tap_straps_rma 188.180s 3105.167us 1 1 100.00
chip_tap_straps_prod 206.870s 2816.279us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 261.340s 3730.140us 1 1 100.00
chip_sw_lc_ctrl_init 0 1 0.00
chip_sw_lc_ctrl_transition 1092.460s 26608.437us 0 1 0.00
chip_sw_lc_ctrl_transitions 0 1 0.00
chip_sw_lc_ctrl_transition 1092.460s 26608.437us 0 1 0.00
chip_sw_lc_ctrl_kmac_req 0 1 0.00
chip_sw_lc_ctrl_transition 1092.460s 26608.437us 0 1 0.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_dpe_key_derivation_prod 2397.760s 14680.678us 1 1 100.00
chip_sw_lc_ctrl_broadcast 18 22 81.82
chip_sw_flash_ctrl_lc_rw_en 248.620s 3571.825us 0 1 0.00
chip_sw_flash_rma_unlocked 8854.290s 97504.739us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 393.850s 4064.789us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 794.170s 8247.900us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 812.480s 10385.400us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 908.400s 8341.121us 0 1 0.00
chip_sw_lc_ctrl_transition 1092.460s 26608.437us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation 2127.000s 13290.149us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 493.280s 10026.659us 1 1 100.00
chip_sw_sram_ctrl_execution_main 781.040s 11996.804us 1 1 100.00
chip_prim_tl_access 338.720s 8671.864us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1682.870s 23599.614us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 552.510s 4701.253us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 518.800s 5414.487us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 601.320s 5181.489us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 548.930s 5700.358us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 612.200s 4910.680us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 563.210s 5516.108us 1 1 100.00
chip_tap_straps_dev 181.750s 2458.982us 1 1 100.00
chip_tap_straps_rma 188.180s 3105.167us 1 1 100.00
chip_tap_straps_prod 206.870s 2816.279us 1 1 100.00
chip_rv_dm_lc_disabled 106.740s 3196.480us 0 1 0.00
chip_lc_scrap 0 4 0.00
chip_sw_lc_ctrl_rma_to_scrap 562.930s 7166.974us 0 1 0.00
chip_sw_lc_ctrl_raw_to_scrap 605.710s 10506.114us 0 1 0.00
chip_sw_lc_ctrl_test_locked0_to_scrap 643.270s 10640.724us 0 1 0.00
chip_sw_lc_ctrl_rand_to_scrap 2446.990s 27350.636us 0 1 0.00
chip_lc_test_locked 0 2 0.00
chip_sw_lc_walkthrough_testunlocks 3600.170s 0.000us 0 1 0.00
chip_rv_dm_lc_disabled 106.740s 3196.480us 0 1 0.00
chip_sw_lc_walkthrough 1 5 20.00
chip_sw_lc_walkthrough_dev 1757.490s 20118.985us 0 1 0.00
chip_sw_lc_walkthrough_prod 1488.780s 25828.399us 0 1 0.00
chip_sw_lc_walkthrough_prodend 1368.020s 16130.293us 1 1 100.00
chip_sw_lc_walkthrough_rma 1008.260s 11444.610us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 3600.170s 0.000us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 253.600s 4544.568us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 336.290s 5901.146us 1 1 100.00
rom_volatile_raw_unlock 90.420s 10.240us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 4261.620s 17891.918us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4370.250s 20257.800us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 773.530s 6735.299us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 773.530s 6735.299us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 773.530s 6735.299us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 442.320s 5005.080us 1 1 100.00
chip_otp_ctrl_init 0 1 0.00
chip_sw_lc_ctrl_transition 1092.460s 26608.437us 0 1 0.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1785.520s 27359.920us 1 1 100.00
chip_sw_otbn_mem_scramble 442.320s 5005.080us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 2127.000s 13290.149us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 506.170s 5219.163us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 290.890s 3129.485us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1785.520s 27359.920us 1 1 100.00
chip_sw_otbn_mem_scramble 442.320s 5005.080us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 2127.000s 13290.149us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 506.170s 5219.163us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 290.890s 3129.485us 1 1 100.00
chip_sw_otp_ctrl_program 0 1 0.00
chip_sw_lc_ctrl_transition 1092.460s 26608.437us 0 1 0.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 678.760s 6429.286us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 261.340s 3730.140us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 4 6 66.67
chip_sw_otp_ctrl_lc_signals_test_unlocked0 393.850s 4064.789us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 794.170s 8247.900us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 812.480s 10385.400us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 908.400s 8341.121us 0 1 0.00
chip_sw_lc_ctrl_transition 1092.460s 26608.437us 0 1 0.00
chip_prim_tl_access 338.720s 8671.864us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 338.720s 8671.864us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1081.470s 9176.256us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 181.770s 3425.459us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 307.860s 3838.901us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 225.470s 4271.840us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 578.360s 8797.312us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 509.950s 7944.510us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1455.180s 30887.389us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 500.020s 6624.196us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 533.720s 9922.748us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 493.690s 4518.979us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 478.840s 6189.431us 1 1 100.00
chip_sw_pwrmgr_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 181.770s 3425.459us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 390.510s 6412.584us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 631.350s 11714.559us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 550.720s 9552.283us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 255.080s 3767.600us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 333.150s 6633.736us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 878.630s 9973.563us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1154.430s 12235.449us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 3070.150s 34743.329us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 277.450s 2829.085us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 558.570s 5817.409us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 493.280s 10026.659us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 493.280s 10026.659us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1154.430s 12235.449us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 333.150s 6633.736us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 478.840s 6189.431us 1 1 100.00
chip_sw_pwrmgr_smoketest 519.350s 7564.901us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 554.260s 6032.377us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 573.880s 6028.903us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 393.430s 4883.114us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1613.720s 15049.293us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 260.680s 3673.072us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 558.570s 5817.409us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1288.480s 8030.889us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 654.490s 4813.559us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 703.860s 5363.918us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 356.040s 4232.384us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 290.890s 3129.485us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 573.880s 6028.903us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 573.880s 6028.903us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 292.800s 3546.031us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 2280.010s 18983.976us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1391.270s 18534.481us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 554.260s 6032.377us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 318.450s 3492.908us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 308.520s 3079.034us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 188.180s 3105.167us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 106.740s 3196.480us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 655.150s 5511.018us 1 1 100.00
chip_plic_all_irqs_10 338.640s 3913.380us 1 1 100.00
chip_plic_all_irqs_20 470.850s 4448.864us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 331.860s 4085.686us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 307.400s 3459.360us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3701.430s 16046.287us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 395.430s 4909.460us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 348.610s 4466.052us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 370.880s 3811.733us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 312.260s 3583.035us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 506.170s 5219.163us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 685.340s 7255.825us 1 1 100.00
chip_sw_sleep_sram_ret_contents 0 2 0.00
chip_sw_sleep_sram_ret_contents_no_scramble 233.800s 3232.156us 0 1 0.00
chip_sw_sleep_sram_ret_contents_scramble 293.780s 4036.980us 0 1 0.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 781.040s 11996.804us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 558.570s 5817.409us 1 1 100.00
chip_sw_data_integrity_escalation 784.960s 7730.631us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1 2 50.00
chip_sw_pwrmgr_sysrst_ctrl_reset 878.630s 9973.563us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1363.870s 24268.323us 0 1 0.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 281.410s 3051.984us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 373.230s 4380.439us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 483.330s 5290.633us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 0 1 0.00
chip_sw_sysrst_ctrl_reset 1363.870s 24268.323us 0 1 0.00
chip_sw_sysrst_ctrl_sleep_reset 0 1 0.00
chip_sw_sysrst_ctrl_reset 1363.870s 24268.323us 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2837.960s 20299.052us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2837.960s 20299.052us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 489.330s 6553.309us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3499.910s 34933.861us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 286.830s 3574.617us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 315.440s 4527.295us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 476.090s 4457.979us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 472.860s 5463.869us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1164.680s 8756.238us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 6486.340s 31947.679us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2049.820s 12043.764us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 303.200s 3855.283us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 268.360s 3242.576us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 302.620s 3831.423us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 12182.670s 73334.503us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1456.420s 7991.169us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 295.400s 5371.866us 0 1 0.00
rom_e2e_jtag_debug_dev 323.850s 4259.070us 0 1 0.00
rom_e2e_jtag_debug_rma 626.070s 7888.819us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 141.840s 3205.873us 0 1 0.00
rom_e2e_jtag_inject_dev 182.000s 3802.670us 0 1 0.00
rom_e2e_jtag_inject_rma 330.940s 5855.054us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 30.171s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 413.130s 4453.636us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 469.070s 3623.452us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 1036.310s 5572.645us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1948.030s 11214.397us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 378.270s 2822.576us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 830.770s 6201.107us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 243.220s 2721.253us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 0 1 0.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 460.820s 7530.363us 0 1 0.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 482.350s 6786.557us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1154.430s 12235.449us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 295.400s 5371.866us 0 1 0.00
rom_e2e_jtag_debug_dev 323.850s 4259.070us 0 1 0.00
rom_e2e_jtag_debug_rma 626.070s 7888.819us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 506.010s 5791.421us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 558.570s 5817.409us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 6736.710s 38466.494us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 6736.710s 38466.494us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 0 1 0.00
chip_sw_spi_device_pinmux_sleep_retention 292.320s 3172.356us 0 1 0.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 537.930s 4303.305us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3713.470s 19067.917us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 4 11 36.36
chip_sival_flash_info_access 398.130s 4077.494us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 77.720s 10.240us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 185.000s 2317.093us 0 1 0.00
chip_sw_otp_ctrl_descrambling 308.000s 3847.513us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 250.210s 3264.508us 0 1 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 12.416s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 338.390s 3413.540us 1 1 100.00
chip_sw_flash_scrambling_smoketest 286.720s 2980.767us 1 1 100.00
ate_bootstrap_flash_erase 800.260s 10010.120us 0 1 0.00
ate_bootstrap_one_frame 10800.148s 0.000us 0 1 0.00
ate_bootstrap_disjoint 339.350s 3830.320us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[RramData]] file empty_test_slot_a_prod_key_*_sim_dv.*.scr.vmem could not be opened for r mode 15 test runs
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 62988747003403808971914975553581719558839544146465904134279327191920293407215 403
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_good_dev 19837893211295616018021535464336305116982272319041893319482001496005832475695 403
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_good_prod 34845224124234784390318215196925537589739134981860417202259799627318470976971 403
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 90478498318536146922968835780492669771448298664938267699517465168295685741054 403
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_good_rma 69808833893086576075418670465216892491287893640432333353864358741873345632529 403
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 93507313411052065227014657082410594357543842107910878865237238819129839353628 426
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 55347316546470954822010402133015702793257026887553993365060179964712296763388 425
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 49418494070382896985659351816005401595116163707417603474453513037737699015160 427
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 14508951399015627447130882107329681744178822701011341624458529600686576842189 426
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 82874767121479847959203971436787200865371289328491444602459631850506646361794 427
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_asm_init_test_unlocked0 7272733662222398203444128236108244271631649109726642569798506861935665014986 379
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_asm_init_dev 47773800097996027867658739644680534074355788138264452701774215569929438836870 379
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_asm_init_prod 12383444412568054591347965715727049930629688266716660214299637774449441101773 379
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_asm_init_prod_end 94387346750787950030956686923739285099387893711831360552680704927504437085806 379
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_asm_init_rma 80500309894013811307871166016856086951951735381632884481309283052288901577070 379
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error 14 test runs
chip_sw_sleep_pin_wake 33478898981703824045572354518308419891620209637444432298690829184236989459206 386
UVM_INFO @ 4370.426646 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_retention 66759483573475575401326978119531757610457043500719460443588286024478133289029 383
UVM_INFO @ 3692.573256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 110762593881878022819712866805504672921767007285478654132834091146259745861414 378
UVM_INFO @ 3172.356124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 12337619852607787565564596494647922830584048023913644087848025749401146308414 381
UVM_INFO @ 4518.979254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 21526530871263650056320939997663210979112185025952760377234419557669662427335 392
UVM_INFO @ 7944.509783 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 46627556031176170234987684870886594499496306801869303949729311504673394520649 381
UVM_INFO @ 3232.155816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 95501835826383065677095400744116623692507009817231344074630545700419793839546 385
UVM_INFO @ 4036.980268 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 5759098541247023097063594514721483969237186302099147369448360940979144430857 376
UVM_INFO @ 3143.827306 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 34643042273079599455380725267952997185745401744457795081058545449349728002024 411
UVM_INFO @ 5278.720464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 106153843069753174360523610540433561153263034789938177902912483668392981774168 378
UVM_INFO @ 4271.839898 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 25581714333021728488940357403140951393956027981451654295772951847447470649814 376
UVM_INFO @ 3264.508382 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 98347258668131843988018821223577971212499147110280054478085119227884294853269 377
UVM_INFO @ 3838.901464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 43465457826322414079428977421384049459186053787098277514088682648942934746774 388
UVM_INFO @ 3079.034280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 64437993839705236432079058547374384549917530699681913145261311088247079728544 391
UVM_INFO @ 4913.906076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access 8 test runs
chip_sw_otp_ctrl_rot_auth_config 98664351403827279785692427316225148297148406741690413189785982460285148471990 381
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 96493897930511453677972552923542361530659716130187096908006466393345558997930 401
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 16512059320004948783514987876231847481471094282808866951040865790190606584040 393
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 44506839150992916685874658168512708317085189321067743559859207012030211737096 393
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 85324094741082049700062025067517723479020889560696452980801869117715242139750 426
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 99749730366052029335658443843323395442475162016359620047336726570552218584352 377
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 75811315170327729196283294586219953174542385865819026766668920399409389530462 377
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 38888914935915890567138214422172751027263793577948933322125121564839866490905 384
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
Offending '(rstreqs[*] && (reset_cause == HwReq))' 6 test runs
chip_sw_flash_ctrl_idle_low_power 39364478435996558475214674400797086456752433981357532947141177882364003022223 376
UVM_ERROR @ 7274.755000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7274.755000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1638174594643136723840434397595612853351425573247916111614413786997918182325 383
UVM_ERROR @ 6633.736000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6633.736000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 50289558297570453667582285758869230838372239375102253162163030473059924718611 382
UVM_ERROR @ 6624.196000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6624.196000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 49926314051635462303068170155118812436450528023949057800482254500425403801488 393
UVM_ERROR @ 8797.312000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8797.312000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_reset 77449229864855980912650650736679884763758028988865602597424557832901426667606 402
UVM_ERROR @ 24268.323000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 24268.323000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 103100267351034425487304045441383828706051605114637428728584059057722000508816 387
UVM_ERROR @ 9922.748000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9922.748000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[RramData]] file empty_test_slot_b_prod_key_*_sim_dv.*.scr.vmem could not be opened for r mode 5 test runs
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 13491803176751508321187651109834182140570057242958702216584784049815345399450 427
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 78302643201358889755390738361493051915485399934969862581619075264528312784690 430
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 35372345304171416871144772289720786491759916010674044844870131376906105683447 429
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 109205625387436694438310403310833629217916446695539954773442938659252629063129 429
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 12828727707340891367522765278120199890765758472880907397810863079977073090010 427
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:884) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl 3 test runs
chip_sw_lc_ctrl_rma_to_scrap 28960513472434499843459765931584415325146441244071884698819812953515161694934 381
UVM_INFO @ 7166.973530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_raw_to_scrap 15345016502846639431770443169492477984244403270668232165781242640140482933750 379
UVM_INFO @ 10506.113824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_test_locked0_to_scrap 109020662637472470069484041426538613759225180177431099683136964273087144807678 379
UVM_INFO @ 10640.724191 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 3 test runs
chip_sw_lc_walkthrough_testunlocks 82020022497756606445614174182029509635558303154755183232881169830000089994357 None
chip_sw_keymgr_dpe_sideload_otbn 17643230576971280901998115460367486925794567258978156676487477495859073853841 None
ate_bootstrap_one_frame 37997337106673008967543753885316231628272505646564319953257054699373686826620 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 2 test runs
chip_sw_lc_walkthrough_dev 87068651061724703425082402864359912622534552447282218888878311758630424824232 437
UVM_INFO @ 20118.985166 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 108099070266142264869275638850246346251944813999745005775132355785973816542610 409
UVM_INFO @ 11444.609536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 2 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 101029721880539943888717946407489945672212898834275876647589708066024749467093 381
UVM_ERROR @ 3767.599636 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3767.599636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 57257874917987174565967360368174815656224470439950399817461777433639323911055 396
UVM_ERROR @ 11714.559440 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 11714.559440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 2 test runs
chip_sw_alert_handler_lpg_sleep_mode_pings 14624669781569388246401469330670896461171608274171724822703542691030070786985 377
UVM_INFO @ 3812.649988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 20851068406280557948113191708714585135462240901444657808039512730358871488369 479
UVM_INFO @ 2999.307612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 70935240786794378440478824819304939068111139436563782727447061618170539599892 None
---- STDERR ----
Another command (pid=2305209) is running. Waiting for it to complete on the server (server_pid=186011)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 102153753379853752322327176931826773892489318803505163488466168921417284677008 None
---- STDERR ----
Another command (pid=382022) is running. Waiting for it to complete on the server (server_pid=186011)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[RramData]] file empty_test_slot_a_test_key_*_sim_dv.*.scr.vmem could not be opened for r mode 2 test runs
rom_volatile_raw_unlock 39534296752973684521935967310990540708141170890402178928339022463758011968388 366
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_raw_unlock 6146789943885507702978127790696018965487518879304085559044614065371288645368 373
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 112327810545707475107560605423980273143845144587576691936210312153396006598719 369
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [inject_scramble_seed_sim_dv(sw/device/tests/sim_dv/inject_scramble_seed.c:60)] CHECK-STATUS-fail: * 1 test run
chip_sw_inject_scramble_seed 78242306963200143836610701217800036899537367506013721051747069499395514682468 377
UVM_INFO @ 4316.314255 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:644) virtual_sequencer [chip_sw_exit_test_unlocked_bootstrap_vseq] Failed to open sw_image file at exit_test_unlocked_bootstrap_sim_dv.*.vmem. 1 test run
chip_sw_exit_test_unlocked_bootstrap 107907525945373610068588982957103525231701010759229879002860171747275820854369 395
UVM_INFO @ 7353.525702 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch 1 test run
chip_sw_spi_device_pass_through_collision 113795025661846992513481865500661288630612678084376336216600512641278278695179 397
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 60538075195022671077172303416586594303837483533506311048777113255987091361026 377
UVM_INFO @ 3571.825296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 31583812668240962155607646492932542695919971653665623156206072453997433651236 408
UVM_INFO @ 8341.120536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(buf_intg_err == '0)' 1 test run
chip_sw_otp_ctrl_escalation 58530892404155909310924530942694927786696191303389476984678254286453410792704 384
UVM_ERROR @ 2721.253450 us: (rram_phy_rd.sv:697) [ASSERT FAILED] IntgError
UVM_INFO @ 2721.253450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:920) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_ctrl_transition 52631508572808346034879309536954412664940045814074676761806048659983655009463 373
UVM_INFO @ 26608.436612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:920) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_ctrl_rand_to_scrap 93796982585517277520423116109253161787544109553383166044600482050129136364812 381
UVM_INFO @ 27350.635794 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:920) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_walkthrough_prod 13376271446037546418194972282746028867898803051804623352497731854345686260123 376
UVM_INFO @ 25828.398955 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 8847107256974098452517716661446053695402198011047946810977369013843932568313 371
UVM_ERROR @ 3425.458620 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 3425.458620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:337) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 56247388564214866341019736179288245248588613380117136513016940864893982864116 400
UVM_INFO @ 34933.860788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:366)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 14683799204184534451820984427751715862366178666136269226255111561426058056586 375
UVM_INFO @ 3034.291948 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 45688390711564816413752993003814783027253505479800498184887810194136938590980 377
UVM_INFO @ 4203.699076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ==== 1 test run
chip_sw_csrng_lc_hw_debug_en_test 43176610123643406500420048880029550055404381056338388751564742483500477301373 392
UVM_INFO @ 4527.873850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:337) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_hmac_multistream 15495486438337716509605521582737753977694218911338668711942336319482268152960 408
UVM_INFO @ 12026.624272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:689) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
chip_tl_errors 29334613139931788590689567955637469083822575594858026211084142814669020807188 284
TL item was: req: (cip_tl_seq_item@82984) { a_addr: 'h104f0 a_data: 'h595fb983 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h36 a_opcode: 'h4 a_user: 'h1b1b4 d_param: 'h0 d_source: 'h36 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3035.899075 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state. 1 test run
chip_sw_clkmgr_reset_frequency 51821660705614380620412615653758032500052693374489999514993719016437739716135 404
UVM_INFO @ 6325.080340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 104162344702175637271266342117163914436781341452974049303688026977955525031580 411
UVM_INFO @ 4453.636387 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: * 1 test run
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 57633276388109758494362587723378549288654921016732078414400471193048719696068 384
UVM_INFO @ 7530.362938 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 84843683934942865109683402511478838734465632373138866668904100204544347153765 288
UVM_INFO @ 3196.479671 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 6672370120365560628566666578068134044274890211438936469970889249067624325654 395
UVM_INFO @ 10915.252553 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 74274551252673545606018597318328417783660847505451360815834161513418543699859 343
UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:644) virtual_sequencer [chip_sw_ate_bootstrap_disjoint_vseq] Failed to open sw_image file at multislot_empty_test_sim_dv.*.vmem. 1 test run
ate_bootstrap_disjoint 52996878279400137601501037183723064198174855346198956068755773658019599707060 371
UVM_INFO @ 3830.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[RramData]] file empty_test_slot_a_unsigned_sim_dv.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_shutdown_output 111159986654024299912301821477207990218047052538797453856009315810909412939313 379
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:375) [csr_utils_pkg::csr_rd_sub.isolation_fork] Timeout waiting to csr_rd chip_reg_block.rv_plic.prio_* (addr=*) 1 test run
chip_csr_mem_rw_with_rand_reset 52152339957483917429046853049945084101522499028520682680157303345837368175774 291
UVM_INFO @ 4382.430060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---