Simulation Results: clkmgr

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.84 %
  • code
  • 98.05 %
  • assert
  • 95.06 %
  • func
  • 85.42 %
  • line
  • 98.48 %
  • branch
  • 98.38 %
  • cond
  • 93.40 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.200s 26.775us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.120s 20.867us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.060s 23.572us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 10.190s 1979.636us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.530s 66.277us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 2.250s 340.126us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.060s 23.572us 1 1 100.00
clkmgr_csr_aliasing 1.530s 66.277us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.860s 28.710us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.160s 27.695us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.090s 36.855us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.070s 42.917us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.200s 26.775us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 4.940s 556.637us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 7.670s 1344.438us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 4.940s 556.637us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 25.010s 5397.949us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.210s 55.929us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.260s 62.015us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.260s 62.015us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 1.120s 20.867us 1 1 100.00
clkmgr_csr_rw 1.060s 23.572us 1 1 100.00
clkmgr_csr_aliasing 1.530s 66.277us 1 1 100.00
clkmgr_same_csr_outstanding 1.280s 35.956us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 1.120s 20.867us 1 1 100.00
clkmgr_csr_rw 1.060s 23.572us 1 1 100.00
clkmgr_csr_aliasing 1.530s 66.277us 1 1 100.00
clkmgr_same_csr_outstanding 1.280s 35.956us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
clkmgr_sec_cm 4.890s 926.753us 1 1 100.00
clkmgr_tl_intg_err 2.020s 80.405us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.960s 86.764us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.960s 86.764us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.960s 86.764us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.960s 86.764us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.630s 199.895us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.020s 80.405us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 4.940s 556.637us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 7.670s 1344.438us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.960s 86.764us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.130s 20.490us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.140s 25.407us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.020s 31.030us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.050s 32.358us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.030s 18.058us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.060s 23.572us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 4.890s 926.753us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.060s 23.572us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.060s 23.572us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 4.890s 926.753us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 6.480s 1594.274us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 15.400s 1234.270us 1 1 100.00