Simulation Results: csrng

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.63 %
  • code
  • 92.23 %
  • assert
  • 94.32 %
  • func
  • 70.34 %
  • block
  • 96.89 %
  • line
  • 97.62 %
  • branch
  • 92.35 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 36.927us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 26.978us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 54.686us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 14.000s 646.915us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 32.978us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 29.101us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 54.686us 1 1 100.00
csrng_csr_aliasing 2.000s 32.978us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 108.916us 1 1 100.00
alerts 1 1 100.00
csrng_alert 5.000s 224.693us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 41.494us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 4.000s 35.423us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 4.000s 35.423us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 88.000s 2126.729us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 19.638us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 20.118us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 228.051us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 228.051us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 26.978us 1 1 100.00
csrng_csr_rw 2.000s 54.686us 1 1 100.00
csrng_csr_aliasing 2.000s 32.978us 1 1 100.00
csrng_same_csr_outstanding 2.000s 57.319us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 26.978us 1 1 100.00
csrng_csr_rw 2.000s 54.686us 1 1 100.00
csrng_csr_aliasing 2.000s 32.978us 1 1 100.00
csrng_same_csr_outstanding 2.000s 57.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 5.000s 258.883us 1 1 100.00
csrng_tl_intg_err 8.000s 942.597us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 2.000s 6.922us 0 1 0.00
csrng_csr_rw 2.000s 54.686us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 5.000s 224.693us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 88.000s 2126.729us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 108.916us 1 1 100.00
csrng_err 3.000s 41.494us 1 1 100.00
csrng_sec_cm 5.000s 258.883us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 108.916us 1 1 100.00
csrng_err 3.000s 41.494us 1 1 100.00
csrng_sec_cm 5.000s 258.883us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 108.916us 1 1 100.00
csrng_err 3.000s 41.494us 1 1 100.00
csrng_sec_cm 5.000s 258.883us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 108.916us 1 1 100.00
csrng_err 3.000s 41.494us 1 1 100.00
csrng_sec_cm 5.000s 258.883us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 108.916us 1 1 100.00
csrng_err 3.000s 41.494us 1 1 100.00
csrng_sec_cm 5.000s 258.883us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 5.000s 224.693us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 108.916us 1 1 100.00
csrng_err 3.000s 41.494us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 88.000s 2126.729us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 5.000s 224.693us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 8.000s 942.597us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 108.916us 1 1 100.00
csrng_err 3.000s 41.494us 1 1 100.00
csrng_sec_cm 5.000s 258.883us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 108.916us 1 1 100.00
csrng_err 3.000s 41.494us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 108.916us 1 1 100.00
csrng_err 3.000s 41.494us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 108.916us 1 1 100.00
csrng_err 3.000s 41.494us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 108.916us 1 1 100.00
csrng_err 3.000s 41.494us 1 1 100.00
csrng_sec_cm 5.000s 258.883us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 108.916us 1 1 100.00
csrng_err 3.000s 41.494us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.064s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:667) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 1868885502256998852738115219629110979834073196174359615923160717866044429726 100
UVM_INFO @ 35423281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 84088513015248507160539353966320296734320011986730778133728153230637444250488 99
UVM_INFO @ 6921501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 16136794248639774799507656319135196461198521720636459981722982291404518846292 None