Simulation Results: edn/edn0

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.64 %
  • code
  • 84.70 %
  • assert
  • 98.26 %
  • func
  • 79.96 %
  • line
  • 97.99 %
  • branch
  • 93.72 %
  • cond
  • 87.87 %
  • toggle
  • 92.82 %
  • FSM
  • 51.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.100s 50.486us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.200s 174.017us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.150s 13.926us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.240s 314.370us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.820s 72.305us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.310s 27.266us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.150s 13.926us 1 1 100.00
edn_csr_aliasing 1.820s 72.305us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.750s 77.988us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.750s 77.988us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.750s 77.988us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.450s 24.074us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.580s 67.129us 1 1 100.00
errs 1 1 100.00
edn_err 1.210s 21.383us 1 1 100.00
disable 2 2 100.00
edn_disable 1.380s 14.556us 1 1 100.00
edn_disable_auto_req_mode 1.650s 201.490us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.360s 99.283us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.240s 56.135us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.240s 25.543us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.250s 287.036us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.250s 287.036us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.200s 174.017us 1 1 100.00
edn_csr_rw 1.150s 13.926us 1 1 100.00
edn_csr_aliasing 1.820s 72.305us 1 1 100.00
edn_same_csr_outstanding 1.410s 25.099us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.200s 174.017us 1 1 100.00
edn_csr_rw 1.150s 13.926us 1 1 100.00
edn_csr_aliasing 1.820s 72.305us 1 1 100.00
edn_same_csr_outstanding 1.410s 25.099us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 10.060s 1961.038us 1 1 100.00
edn_tl_intg_err 2.420s 369.218us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.290s 29.133us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.580s 67.129us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.060s 1961.038us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.060s 1961.038us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 10.060s 1961.038us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 10.060s 1961.038us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.580s 67.129us 1 1 100.00
edn_sec_cm 10.060s 1961.038us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.580s 67.129us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.420s 369.218us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 56.460s 9591.137us 1 1 100.00