Simulation Results: edn/edn1

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.48 %
  • code
  • 83.16 %
  • assert
  • 98.18 %
  • func
  • 81.09 %
  • line
  • 98.25 %
  • branch
  • 93.94 %
  • cond
  • 91.62 %
  • toggle
  • 87.68 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.190s 18.699us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.170s 21.732us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.130s 16.700us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.120s 132.313us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.860s 97.119us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.170s 19.617us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.130s 16.700us 1 1 100.00
edn_csr_aliasing 1.860s 97.119us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.740s 69.846us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.740s 69.846us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.740s 69.846us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.970s 70.674us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.540s 58.945us 1 1 100.00
errs 1 1 100.00
edn_err 1.260s 27.060us 1 1 100.00
disable 2 2 100.00
edn_disable 1.050s 28.593us 1 1 100.00
edn_disable_auto_req_mode 1.410s 72.551us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 9.360s 487.686us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.060s 17.898us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.980s 198.236us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.810s 214.033us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.810s 214.033us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.170s 21.732us 1 1 100.00
edn_csr_rw 1.130s 16.700us 1 1 100.00
edn_csr_aliasing 1.860s 97.119us 1 1 100.00
edn_same_csr_outstanding 1.710s 102.612us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.170s 21.732us 1 1 100.00
edn_csr_rw 1.130s 16.700us 1 1 100.00
edn_csr_aliasing 1.860s 97.119us 1 1 100.00
edn_same_csr_outstanding 1.710s 102.612us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.460s 173.353us 1 1 100.00
edn_tl_intg_err 1.750s 194.069us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.110s 93.942us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.540s 58.945us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.460s 173.353us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.460s 173.353us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.460s 173.353us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.460s 173.353us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.540s 58.945us 1 1 100.00
edn_sec_cm 3.460s 173.353us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.540s 58.945us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.750s 194.069us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 111.430s 4580.013us 1 1 100.00