| V1 |
|
83.33% |
| V2 |
|
93.75% |
| V2S |
|
85.71% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| entropy_src_smoke | 2.000s | 110.211us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| entropy_src_csr_hw_reset | 1.000s | 90.263us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| entropy_src_csr_rw | 1.000s | 22.702us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| entropy_src_csr_bit_bash | 6.000s | 419.002us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| entropy_src_csr_aliasing | 3.000s | 230.629us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| entropy_src_csr_mem_rw_with_rand_reset | 1.000s | 12.664us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| entropy_src_csr_rw | 1.000s | 22.702us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 3.000s | 230.629us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 2 | 3 | 66.67 | |||
| entropy_src_smoke | 2.000s | 110.211us | 1 | 1 | 100.00 | |
| entropy_src_rng | 136.000s | 13178.937us | 1 | 1 | 100.00 | |
| entropy_src_fw_ov | 3601.000s | 0.000us | 0 | 1 | 0.00 | |
| firmware_mode | 0 | 1 | 0.00 | |||
| entropy_src_fw_ov | 3601.000s | 0.000us | 0 | 1 | 0.00 | |
| rng_mode | 1 | 1 | 100.00 | |||
| entropy_src_rng | 136.000s | 13178.937us | 1 | 1 | 100.00 | |
| rng_max_rate | 1 | 1 | 100.00 | |||
| entropy_src_rng_max_rate | 236.000s | 14105.449us | 1 | 1 | 100.00 | |
| health_checks | 1 | 1 | 100.00 | |||
| entropy_src_rng | 136.000s | 13178.937us | 1 | 1 | 100.00 | |
| conditioning | 1 | 1 | 100.00 | |||
| entropy_src_rng | 136.000s | 13178.937us | 1 | 1 | 100.00 | |
| interrupts | 2 | 2 | 100.00 | |||
| entropy_src_rng | 136.000s | 13178.937us | 1 | 1 | 100.00 | |
| entropy_src_intr | 3.000s | 43.518us | 1 | 1 | 100.00 | |
| alerts | 2 | 2 | 100.00 | |||
| entropy_src_rng | 136.000s | 13178.937us | 1 | 1 | 100.00 | |
| entropy_src_functional_alerts | 4.000s | 183.377us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| entropy_src_stress_all | 53.000s | 14382.083us | 1 | 1 | 100.00 | |
| functional_errors | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 66.060us | 1 | 1 | 100.00 | |
| firmware_ov_read_contiguous_data | 1 | 1 | 100.00 | |||
| entropy_src_fw_ov_contiguous | 3.000s | 118.623us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| entropy_src_intr_test | 2.000s | 29.441us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| entropy_src_alert_test | 1.000s | 127.235us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 3.000s | 48.615us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 3.000s | 48.615us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 1.000s | 90.263us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 1.000s | 22.702us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 3.000s | 230.629us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 3.000s | 154.345us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 1.000s | 90.263us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 1.000s | 22.702us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 3.000s | 230.629us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 3.000s | 154.345us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| entropy_src_sec_cm | 2.000s | 53.234us | 1 | 1 | 100.00 | |
| entropy_src_tl_intg_err | 3.000s | 642.502us | 1 | 1 | 100.00 | |
| sec_cm_config_regwen | 2 | 2 | 100.00 | |||
| entropy_src_rng | 136.000s | 13178.937us | 1 | 1 | 100.00 | |
| entropy_src_cfg_regwen | 1.000s | 51.649us | 1 | 1 | 100.00 | |
| sec_cm_config_mubi | 1 | 1 | 100.00 | |||
| entropy_src_rng | 136.000s | 13178.937us | 1 | 1 | 100.00 | |
| sec_cm_config_redun | 1 | 1 | 100.00 | |||
| entropy_src_rng | 136.000s | 13178.937us | 1 | 1 | 100.00 | |
| sec_cm_intersig_mubi | 1 | 2 | 50.00 | |||
| entropy_src_rng | 136.000s | 13178.937us | 1 | 1 | 100.00 | |
| entropy_src_fw_ov | 3601.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 66.060us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 53.234us | 1 | 1 | 100.00 | |
| sec_cm_ack_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 66.060us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 53.234us | 1 | 1 | 100.00 | |
| sec_cm_rng_bkgn_chk | 1 | 1 | 100.00 | |||
| entropy_src_rng | 136.000s | 13178.937us | 1 | 1 | 100.00 | |
| sec_cm_fifo_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 66.060us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 53.234us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 66.060us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 53.234us | 1 | 1 | 100.00 | |
| sec_cm_ctr_local_esc | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 66.060us | 1 | 1 | 100.00 | |
| sec_cm_esfinal_rdata_bus_consistency | 1 | 1 | 100.00 | |||
| entropy_src_functional_alerts | 4.000s | 183.377us | 1 | 1 | 100.00 | |
| sec_cm_tile_link_bus_integrity | 1 | 1 | 100.00 | |||
| entropy_src_tl_intg_err | 3.000s | 642.502us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| external_health_tests | 1 | 1 | 100.00 | |||
| entropy_src_rng_with_xht_rsps | 253.000s | 14061.365us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| entropy_src_stress_all_with_rand_reset | 8.000s | 490.616us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_hi_threshold | 1 test run | |||
| entropy_src_stress_all_with_rand_reset | 24467590696992079826334131790471608082937774777451636642094855610300261676943 | 118 |
UVM_INFO @ 490616484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 1 test run | |||
| entropy_src_fw_ov | 54024087482588865975331130510582277085507077012708802107965196921353443365717 | None | ||
| UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_lo_total_fails | 1 test run | |||
| entropy_src_csr_mem_rw_with_rand_reset | 31596869920307577119143646054253174066286375426782663787094801958252875039550 | 113 |
UVM_INFO @ 12664330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|