Simulation Results: flash_ctrl

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.24 %
  • code
  • 92.56 %
  • assert
  • 94.64 %
  • func
  • 95.51 %
  • line
  • 95.88 %
  • branch
  • 96.67 %
  • cond
  • 93.20 %
  • toggle
  • 92.70 %
  • FSM
  • 84.35 %
Validation stages
V1
100.00%
V2
91.38%
V2S
91.67%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 257.140s 31.756us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 114.420s 32.106us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 166.440s 42.093us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 77.290s 231.629us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 138.520s 22732.873us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 120.510s 723.733us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 85.250s 201.660us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 77.290s 231.629us 1 1 100.00
flash_ctrl_csr_aliasing 120.510s 723.733us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 61.850s 29.056us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 62.850s 65.606us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 116.000s 42.157us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 541.680s 86.901us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1741.200s 341986.090us 1 1 100.00
flash_ctrl_hw_rma_reset 863.460s 290308.465us 1 1 100.00
flash_ctrl_lcmgr_intg 61.370s 25.392us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 3290.410s 279902.989us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 1458.200s 2766.934us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 59.610s 34.344us 1 1 100.00
full_memory_access 0 1 0.00
flash_ctrl_full_mem_access 2891.440s 527715.382us 0 1 0.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 514.700s 105.310us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 122.820s 34.939us 1 1 100.00
flash_ctrl_rw_evict_all_en 122.530s 42.953us 1 1 100.00
flash_ctrl_re_evict 126.880s 73.920us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 456.970s 76.347us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 456.970s 76.347us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 199.140s 32267.377us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 91.730s 314.982us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 567.820s 40.231us 1 1 100.00
error_mp 0 1 0.00
flash_ctrl_error_mp 3600.144s 0.000us 0 1 0.00
error_prog_win 0 1 0.00
flash_ctrl_error_prog_win 3600.131s 0.000us 0 1 0.00
error_prog_type 0 1 0.00
flash_ctrl_error_prog_type 3600.138s 0.000us 0 1 0.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 68.840s 21.283us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 179.880s 1187.923us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 105.850s 32.288us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 91.970s 50.020us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 2074.450s 685.178us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 170.390s 23861.870us 1 1 100.00
flash_ctrl_otp_reset 545.090s 39.479us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1741.200s 341986.090us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 277.460s 2453.979us 1 1 100.00
flash_ctrl_intr_wr 105.730s 4389.405us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 278.840s 22875.789us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 247.220s 54679.240us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 131.250s 2064.165us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 145.160s 2087.323us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 92.780s 113.511us 1 1 100.00
flash_ctrl_ro_derr 186.290s 3264.409us 1 1 100.00
flash_ctrl_rw_derr 232.750s 20798.071us 1 1 100.00
flash_ctrl_derr_detect 576.710s 699.195us 1 1 100.00
flash_ctrl_integrity 502.420s 4727.853us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 90.150s 30.341us 1 1 100.00
flash_ctrl_ro_serr 178.350s 1054.061us 1 1 100.00
flash_ctrl_rw_serr 238.830s 3925.104us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 122.530s 2865.170us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 134.920s 3910.105us 1 1 100.00
scramble 4 5 80.00
flash_ctrl_wo 164.030s 9931.687us 1 1 100.00
flash_ctrl_write_word_sweep 67.060s 83.716us 1 1 100.00
flash_ctrl_read_word_sweep 57.240s 28.945us 1 1 100.00
flash_ctrl_ro 145.150s 2929.305us 1 1 100.00
flash_ctrl_rw 3602.748s 0.000us 0 1 0.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 83.860s 1352.391us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 725.430s 79174.931us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 182.130s 10028.379us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 76.380s 64.601us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 65.940s 33.178us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 62.200s 300.209us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 62.200s 300.209us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 166.440s 42.093us 1 1 100.00
flash_ctrl_csr_rw 77.290s 231.629us 1 1 100.00
flash_ctrl_csr_aliasing 120.510s 723.733us 1 1 100.00
flash_ctrl_same_csr_outstanding 123.090s 66.578us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 166.440s 42.093us 1 1 100.00
flash_ctrl_csr_rw 77.290s 231.629us 1 1 100.00
flash_ctrl_csr_aliasing 120.510s 723.733us 1 1 100.00
flash_ctrl_same_csr_outstanding 123.090s 66.578us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 177.750s 187.826us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 177.750s 187.826us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 177.750s 187.826us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 177.750s 187.826us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 345.870s 107.216us 1 1 100.00
tl_intg_err 1 2 50.00
flash_ctrl_sec_cm 10800.113s 0.000us 0 1 0.00
flash_ctrl_tl_intg_err 3409.490s 669.994us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 3409.490s 669.994us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 3409.490s 669.994us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 125.490s 72.581us 1 1 100.00
flash_ctrl_wr_intg 61.260s 51.123us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 257.140s 31.756us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 545.090s 39.479us 1 1 100.00
flash_ctrl_disable 105.850s 32.288us 1 1 100.00
flash_ctrl_sec_info_access 105.140s 2972.015us 1 1 100.00
flash_ctrl_connect 91.970s 50.020us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 71.650s 47.022us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 77.290s 231.629us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 177.750s 187.826us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 77.290s 231.629us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 177.750s 187.826us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 77.290s 231.629us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 177.750s 187.826us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 105.850s 32.288us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 125.490s 72.581us 1 1 100.00
flash_ctrl_access_after_disable 97.170s 72.509us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 136.000s 66.903us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 105.850s 32.288us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 91.730s 314.982us 1 1 100.00
sec_cm_mem_scramble 0 1 0.00
flash_ctrl_rw 3602.748s 0.000us 0 1 0.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 238.830s 3925.104us 1 1 100.00
flash_ctrl_rw_derr 232.750s 20798.071us 1 1 100.00
flash_ctrl_integrity 502.420s 4727.853us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1741.200s 341986.090us 1 1 100.00
sec_cm_ctrl_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 10800.113s 0.000us 0 1 0.00
sec_cm_phy_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 10800.113s 0.000us 0 1 0.00
sec_cm_phy_prog_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 10800.113s 0.000us 0 1 0.00
sec_cm_ctr_redun 0 1 0.00
flash_ctrl_sec_cm 10800.113s 0.000us 0 1 0.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 68.210s 883.206us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 62.560s 38.254us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 63.200s 24.722us 1 1 100.00
sec_cm_fifo_ctr_redun 0 1 0.00
flash_ctrl_sec_cm 10800.113s 0.000us 0 1 0.00
sec_cm_mem_tl_lc_gate_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 10800.113s 0.000us 0 1 0.00
sec_cm_prog_tl_lc_gate_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 10800.113s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 188.570s 126.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 469.810s 1029.033us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 5 test runs
flash_ctrl_error_prog_type 113811966115990224610772520389726552740520645033473511598725578810582327127695 None
flash_ctrl_error_prog_win 56051973125651086328752909913865239049035258394895345237952745676339334430058 None
flash_ctrl_error_mp 22146348653189522280649612322598973811545600055386502983550342415541488798470 None
flash_ctrl_rw 59491354423504783392585393144528592492283680763733907001232911246419987198926 None
flash_ctrl_sec_cm 108783955213567816030768787818135925459777472755399984836849265296267131853747 None
UVM_ERROR (flash_ctrl_scoreboard.sv:735) [scoreboard] Check failed exp_data_part[addr] == data (* [*] vs * [*]) read addr:* data: * 1 test run
flash_ctrl_full_mem_access 2760587806313003224739156417185745097075828636204511300113958606515753037475 275581
UVM_INFO @ 527715381.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---