Simulation Results: hmac

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.33 %
  • code
  • 86.75 %
  • assert
  • 97.60 %
  • func
  • 41.65 %
  • line
  • 99.49 %
  • branch
  • 98.37 %
  • cond
  • 95.58 %
  • toggle
  • 46.17 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.000s 2017.061us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.760s 71.667us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.680s 31.167us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.220s 2660.479us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.450s 225.884us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.810s 73.789us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.680s 31.167us 1 1 100.00
hmac_csr_aliasing 2.450s 225.884us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 57.210s 13570.510us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 56.520s 2105.381us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 164.610s 7584.029us 1 1 100.00
hmac_test_sha384_vectors 19.330s 785.076us 1 1 100.00
hmac_test_sha512_vectors 20.370s 517.636us 1 1 100.00
hmac_test_hmac256_vectors 9.750s 386.075us 1 1 100.00
hmac_test_hmac384_vectors 7.190s 1794.053us 1 1 100.00
hmac_test_hmac512_vectors 8.960s 723.233us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 10.690s 3155.945us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 876.530s 123161.050us 1 1 100.00
error 1 1 100.00
hmac_error 20.020s 5568.921us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 95.970s 8096.554us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.000s 2017.061us 1 1 100.00
hmac_long_msg 57.210s 13570.510us 1 1 100.00
hmac_back_pressure 56.520s 2105.381us 1 1 100.00
hmac_datapath_stress 876.530s 123161.050us 1 1 100.00
hmac_burst_wr 10.690s 3155.945us 1 1 100.00
hmac_stress_all 76.870s 30192.810us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.000s 2017.061us 1 1 100.00
hmac_long_msg 57.210s 13570.510us 1 1 100.00
hmac_back_pressure 56.520s 2105.381us 1 1 100.00
hmac_datapath_stress 876.530s 123161.050us 1 1 100.00
hmac_wipe_secret 95.970s 8096.554us 1 1 100.00
hmac_test_sha256_vectors 164.610s 7584.029us 1 1 100.00
hmac_test_sha384_vectors 19.330s 785.076us 1 1 100.00
hmac_test_sha512_vectors 20.370s 517.636us 1 1 100.00
hmac_test_hmac256_vectors 9.750s 386.075us 1 1 100.00
hmac_test_hmac384_vectors 7.190s 1794.053us 1 1 100.00
hmac_test_hmac512_vectors 8.960s 723.233us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.000s 2017.061us 1 1 100.00
hmac_long_msg 57.210s 13570.510us 1 1 100.00
hmac_back_pressure 56.520s 2105.381us 1 1 100.00
hmac_datapath_stress 876.530s 123161.050us 1 1 100.00
hmac_burst_wr 10.690s 3155.945us 1 1 100.00
hmac_error 20.020s 5568.921us 1 1 100.00
hmac_wipe_secret 95.970s 8096.554us 1 1 100.00
hmac_test_sha256_vectors 164.610s 7584.029us 1 1 100.00
hmac_test_sha384_vectors 19.330s 785.076us 1 1 100.00
hmac_test_sha512_vectors 20.370s 517.636us 1 1 100.00
hmac_test_hmac256_vectors 9.750s 386.075us 1 1 100.00
hmac_test_hmac384_vectors 7.190s 1794.053us 1 1 100.00
hmac_test_hmac512_vectors 8.960s 723.233us 1 1 100.00
hmac_stress_all 76.870s 30192.810us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 76.870s 30192.810us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.590s 18.136us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.600s 17.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.250s 2420.325us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.250s 2420.325us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.760s 71.667us 1 1 100.00
hmac_csr_rw 0.680s 31.167us 1 1 100.00
hmac_csr_aliasing 2.450s 225.884us 1 1 100.00
hmac_same_csr_outstanding 1.690s 431.518us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.760s 71.667us 1 1 100.00
hmac_csr_rw 0.680s 31.167us 1 1 100.00
hmac_csr_aliasing 2.450s 225.884us 1 1 100.00
hmac_same_csr_outstanding 1.690s 431.518us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.100s 1003.736us 1 1 100.00
hmac_tl_intg_err 1.550s 279.709us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.550s 279.709us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.000s 2017.061us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.190s 118.051us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 115.540s 32935.732us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.750s 18.210us 1 1 100.00