Simulation Results

Simulation Results: i2c

19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.28 %

code
78.67 %

assert
97.46 %

func
79.70 %

line
96.75 %

branch
92.69 %

cond
84.63 %

toggle
74.04 %

FSM
45.24 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	14.280s	1444.625us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	6.460s	3329.798us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.850s	135.290us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.770s	25.773us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	1.920s	796.685us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.060s	846.259us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.010s	67.733us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.770s	25.773us	1	1	100.00
	i2c_csr_aliasing	1.060s	846.259us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.730s	81.256us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	71.680s	23479.320us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	197.110s	71859.342us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.730s	56.694us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	77.190s	10740.502us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	50.970s	12903.421us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.740s	518.361us	1	1	100.00
	i2c_host_fifo_fmt_empty	4.660s	889.408us	1	1	100.00
	i2c_host_fifo_reset_rx	2.100s	685.380us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	37.030s	11170.579us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	5.970s	2101.130us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.860s	99.291us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.810s	1911.390us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	53.730s	21901.088us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.560s	650.074us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	25.840s	3401.619us	1	1	100.00
	i2c_target_intr_smoke	4.280s	2063.046us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.330s	834.133us	1	1	100.00
	i2c_target_fifo_reset_tx	1.070s	190.398us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	91.260s	51415.921us	1	1	100.00
	i2c_target_stress_rd	25.840s	3401.619us	1	1	100.00
	i2c_target_intr_stress_wr	77.440s	14288.024us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	3.790s	4606.527us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	10.800s	4346.887us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.520s	708.776us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	11.610s	10258.290us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.800s	1735.532us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.870s	461.582us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	197.110s	71859.342us	1	1	100.00
	i2c_host_perf_precise	0.920s	165.125us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	5.970s	2101.130us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.240s	246.964us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.780s	1728.507us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.870s	1696.647us	1	1	100.00
	i2c_target_nack_txstretch	1.280s	1705.033us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	3.030s	1044.010us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.870s	1999.989us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.860s	27.815us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.820s	17.703us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.730s	73.669us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.730s	73.669us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.850s	135.290us	1	1	100.00
	i2c_csr_rw	0.770s	25.773us	1	1	100.00
	i2c_csr_aliasing	1.060s	846.259us	1	1	100.00
	i2c_same_csr_outstanding	0.960s	32.305us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.850s	135.290us	1	1	100.00
	i2c_csr_rw	0.770s	25.773us	1	1	100.00
	i2c_csr_aliasing	1.060s	846.259us	1	1	100.00
	i2c_same_csr_outstanding	0.960s	32.305us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.350s	86.516us	1	1	100.00
	i2c_sec_cm	0.990s	39.973us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.350s	86.516us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	3.720s	308.391us	1
target_error_intr				1
	i2c_target_unexp_stop	1.350s	343.921us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	2.070s	155.123us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				4 test runs
	i2c_host_error_intr	29204274133229004379177261850816259512164939490669998395564123882725728145511	94	UVM_INFO @ 81256181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	41649992014492803612724930456372528185059521829974644061624053152913475532135	125	UVM_INFO @ 23479320217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	22426577804591243511405611742109242129931533196565558167396971478773255293476	91	UVM_INFO @ 155123347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	17817790115587927317632919032916712409547039419433477418163982996534199302758	87	UVM_INFO @ 99290813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	108645754033868492652349289131910222121902205421774772673932374023371001055163	90	UVM_INFO @ 1911389680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	84620464145088699846122150305233983010335388703371725403169788945466338068399	84	UVM_INFO @ 343920921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	37487493235864021842040296187604534084802086536644473142383305602145245609310	85	UVM_INFO @ 10258290189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	56805939306623475043775069889948802357013485933678896573691956073256051884123	93	UVM_INFO @ 308390701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---