Simulation Results: keymgr_dpe/earlgrey

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 64.84 %
  • code
  • 82.31 %
  • assert
  • 97.44 %
  • func
  • 14.77 %
  • line
  • 97.60 %
  • branch
  • 93.67 %
  • cond
  • 86.46 %
  • toggle
  • 58.12 %
  • FSM
  • 75.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_dpe_smoke 10.200s 773.222us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 0.830s 45.569us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 0.860s 81.752us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 4.050s 813.381us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 4.750s 355.541us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 0.920s 15.216us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_dpe_csr_rw 0.860s 81.752us 1 1 100.00
keymgr_dpe_csr_aliasing 4.750s 355.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 0.790s 38.537us 1 1 100.00
alert_test 1 1 100.00
keymgr_dpe_alert_test 0.830s 47.793us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 2.680s 52.282us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 2.680s 52.282us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_dpe_csr_hw_reset 0.830s 45.569us 1 1 100.00
keymgr_dpe_csr_rw 0.860s 81.752us 1 1 100.00
keymgr_dpe_csr_aliasing 4.750s 355.541us 1 1 100.00
keymgr_dpe_same_csr_outstanding 1.260s 89.734us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_dpe_csr_hw_reset 0.830s 45.569us 1 1 100.00
keymgr_dpe_csr_rw 0.860s 81.752us 1 1 100.00
keymgr_dpe_csr_aliasing 4.750s 355.541us 1 1 100.00
keymgr_dpe_same_csr_outstanding 1.260s 89.734us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
keymgr_dpe_sec_cm 9.700s 3170.841us 1 1 100.00
keymgr_dpe_tl_intg_err 1.890s 460.537us 1 1 100.00
shadow_reg_update_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.970s 362.645us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.970s 362.645us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.970s 362.645us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.970s 362.645us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 1.930s 96.263us 0 1 0.00
prim_count_check 1 1 100.00
keymgr_dpe_sec_cm 9.700s 3170.841us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_dpe_sec_cm 9.700s 3170.841us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(reg2hw.control_shadowed.slot_dst_sel.q < NumInstHwSlot)' 1 test run
keymgr_dpe_shadow_reg_errors 77849601068406597832640637727991261629748188130262173340391769580339778040649 83
UVM_ERROR @ 362644894 ps: (keymgr_dpe.sv:321) [ASSERT FAILED] DstSelInRange_A
UVM_INFO @ 362644894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(reg2hw.control_shadowed.slot_src_sel.q < NumInstHwSlot)' 1 test run
keymgr_dpe_shadow_reg_errors_with_csr_rw 35455079839808429869806762759997593859243595938245525683444548955113140849686 83
UVM_ERROR @ 96262893 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 96262893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---