Simulation Results: lc_ctrl/volatile_unlock_disabled

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.55 %
  • code
  • 83.66 %
  • assert
  • 94.97 %
  • func
  • 93.01 %
  • line
  • 97.24 %
  • branch
  • 93.61 %
  • cond
  • 79.52 %
  • toggle
  • 85.29 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.780s 46.065us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.020s 19.102us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.740s 38.049us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.380s 207.028us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 41.978us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.460s 44.488us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.740s 38.049us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 41.978us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 1.440s 42.392us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.130s 195.874us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.850s 18.271us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.230s 79.226us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.510s 253.761us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.750s 1781.858us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.510s 253.761us 1 1 100.00
lc_ctrl_prog_failure 2.230s 79.226us 1 1 100.00
lc_ctrl_errors 4.750s 1781.858us 1 1 100.00
lc_ctrl_security_escalation 3.650s 587.005us 1 1 100.00
lc_ctrl_jtag_state_failure 16.070s 19633.040us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.050s 563.571us 1 1 100.00
lc_ctrl_jtag_errors 14.410s 1355.728us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.960s 758.716us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.090s 585.309us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.050s 563.571us 1 1 100.00
lc_ctrl_jtag_errors 14.410s 1355.728us 1 1 100.00
lc_ctrl_jtag_access 1.260s 166.692us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.110s 1690.370us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.410s 1713.128us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.070s 56.742us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.010s 13951.605us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.190s 218.293us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.060s 19.003us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.770s 430.415us 1 1 100.00
lc_ctrl_jtag_alert_test 1.140s 1215.626us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.260s 1797.352us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.880s 45.499us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 44.620s 7885.290us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.710s 15.555us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.760s 140.475us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.760s 140.475us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 19.102us 1 1 100.00
lc_ctrl_csr_rw 0.740s 38.049us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 41.978us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.760s 50.708us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 19.102us 1 1 100.00
lc_ctrl_csr_rw 0.740s 38.049us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 41.978us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.760s 50.708us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.940s 218.274us 1 1 100.00
lc_ctrl_tl_intg_err 1.630s 120.573us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.630s 120.573us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.130s 195.874us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.510s 253.761us 1 1 100.00
lc_ctrl_sec_cm 5.940s 218.274us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.510s 253.761us 1 1 100.00
lc_ctrl_sec_cm 5.940s 218.274us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.510s 253.761us 1 1 100.00
lc_ctrl_sec_cm 5.940s 218.274us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.510s 253.761us 1 1 100.00
lc_ctrl_sec_cm 5.940s 218.274us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.510s 253.761us 1 1 100.00
lc_ctrl_sec_cm 5.940s 218.274us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.510s 253.761us 1 1 100.00
lc_ctrl_sec_cm 5.940s 218.274us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.510s 253.761us 1 1 100.00
lc_ctrl_sec_cm 5.940s 218.274us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.510s 253.761us 1 1 100.00
lc_ctrl_sec_cm 5.940s 218.274us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.650s 587.005us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 1.440s 42.392us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.090s 585.309us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.090s 677.100us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.090s 677.100us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.670s 887.465us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.220s 1183.610us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.220s 1183.610us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 12.920s 983.383us 1 1 100.00