Simulation Results: lc_ctrl/volatile_unlock_enabled

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.97 %
  • code
  • 84.16 %
  • assert
  • 94.83 %
  • func
  • 93.91 %
  • line
  • 97.04 %
  • branch
  • 93.29 %
  • cond
  • 79.22 %
  • toggle
  • 86.77 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.770s 40.484us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.760s 50.379us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.910s 32.595us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.270s 367.487us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 19.881us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.830s 83.815us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.910s 32.595us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 19.881us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 1.680s 72.169us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.400s 1084.499us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.880s 40.744us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.650s 83.616us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.900s 1093.253us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.400s 688.778us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.900s 1093.253us 1 1 100.00
lc_ctrl_prog_failure 1.650s 83.616us 1 1 100.00
lc_ctrl_errors 7.400s 688.778us 1 1 100.00
lc_ctrl_security_escalation 3.640s 474.995us 1 1 100.00
lc_ctrl_jtag_state_failure 21.210s 1377.626us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.930s 854.443us 1 1 100.00
lc_ctrl_jtag_errors 40.630s 4940.727us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.310s 750.687us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.230s 420.149us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.930s 854.443us 1 1 100.00
lc_ctrl_jtag_errors 40.630s 4940.727us 1 1 100.00
lc_ctrl_jtag_access 6.190s 3393.358us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.090s 4655.943us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.370s 121.823us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.010s 70.911us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.520s 933.713us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.660s 2703.527us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.600s 167.588us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.200s 49.442us 1 1 100.00
lc_ctrl_jtag_alert_test 0.860s 200.685us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.750s 1708.069us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.830s 15.043us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 32.130s 7072.478us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.850s 371.667us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.330s 89.350us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.330s 89.350us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.760s 50.379us 1 1 100.00
lc_ctrl_csr_rw 0.910s 32.595us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 19.881us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.170s 188.911us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.760s 50.379us 1 1 100.00
lc_ctrl_csr_rw 0.910s 32.595us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 19.881us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.170s 188.911us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.810s 121.333us 1 1 100.00
lc_ctrl_tl_intg_err 1.770s 450.048us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.770s 450.048us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.400s 1084.499us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.900s 1093.253us 1 1 100.00
lc_ctrl_sec_cm 4.810s 121.333us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.900s 1093.253us 1 1 100.00
lc_ctrl_sec_cm 4.810s 121.333us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.900s 1093.253us 1 1 100.00
lc_ctrl_sec_cm 4.810s 121.333us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.900s 1093.253us 1 1 100.00
lc_ctrl_sec_cm 4.810s 121.333us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.900s 1093.253us 1 1 100.00
lc_ctrl_sec_cm 4.810s 121.333us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.900s 1093.253us 1 1 100.00
lc_ctrl_sec_cm 4.810s 121.333us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.900s 1093.253us 1 1 100.00
lc_ctrl_sec_cm 4.810s 121.333us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.900s 1093.253us 1 1 100.00
lc_ctrl_sec_cm 4.810s 121.333us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.640s 474.995us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 1.680s 72.169us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.230s 420.149us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.270s 982.321us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.270s 982.321us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.470s 1067.918us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.750s 1609.837us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.750s 1609.837us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 42.670s 3356.360us 1 1 100.00