Simulation Results: otbn

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.04 %
  • code
  • 81.92 %
  • assert
  • 89.90 %
  • func
  • 98.31 %
  • block
  • 97.75 %
  • line
  • 97.96 %
  • branch
  • 81.97 %
  • toggle
  • 81.54 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 12.000s 72.608us 1 1 100.00
otbn_smoke_vectorized 9.000s 33.828us 1 1 100.00
single_binary 1 1 100.00
otbn_single 10.000s 101.538us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 25.774us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 6.000s 15.208us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 11.000s 169.036us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 5.000s 42.732us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 9.000s 853.565us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 6.000s 15.208us 1 1 100.00
otbn_csr_aliasing 5.000s 42.732us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 135.000s 6180.049us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 35.000s 1286.446us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 50.000s 114.512us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 76.000s 326.017us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 56.000s 728.168us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 94.000s 271.433us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 16.000s 92.648us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 13.000s 26.866us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 12.000s 25.584us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 7.000s 21.918us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 5.000s 19.592us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 8.000s 150.229us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 8.000s 150.229us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 5.000s 25.774us 1 1 100.00
otbn_csr_rw 6.000s 15.208us 1 1 100.00
otbn_csr_aliasing 5.000s 42.732us 1 1 100.00
otbn_same_csr_outstanding 7.000s 54.834us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 5.000s 25.774us 1 1 100.00
otbn_csr_rw 6.000s 15.208us 1 1 100.00
otbn_csr_aliasing 5.000s 42.732us 1 1 100.00
otbn_same_csr_outstanding 7.000s 54.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 13.000s 27.380us 1 1 100.00
otbn_dmem_err 10.000s 18.781us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 14.000s 145.529us 1 1 100.00
otbn_controller_ispr_rdata_err 10.000s 13.889us 1 1 100.00
otbn_mac_bignum_acc_err 15.000s 65.206us 1 1 100.00
otbn_urnd_err 7.000s 25.618us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 7.000s 18.655us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 13.000s 31.809us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 7.000s 31.240us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 414.000s 4410.725us 1 1 100.00
otbn_tl_intg_err 26.000s 317.229us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 68.000s 201.140us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 414.000s 4410.725us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 414.000s 4410.725us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 12.000s 72.608us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 10.000s 18.781us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 13.000s 27.380us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 26.000s 317.229us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 16.000s 92.648us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 13.000s 27.380us 1 1 100.00
otbn_dmem_err 10.000s 18.781us 1 1 100.00
otbn_zero_state_err_urnd 13.000s 26.866us 1 1 100.00
otbn_illegal_mem_acc 7.000s 18.655us 1 1 100.00
otbn_sec_cm 414.000s 4410.725us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 414.000s 4410.725us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 10.000s 101.538us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 13.000s 27.380us 1 1 100.00
otbn_dmem_err 10.000s 18.781us 1 1 100.00
otbn_zero_state_err_urnd 13.000s 26.866us 1 1 100.00
otbn_illegal_mem_acc 7.000s 18.655us 1 1 100.00
otbn_sec_cm 414.000s 4410.725us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 414.000s 4410.725us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 16.000s 92.648us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 13.000s 27.380us 1 1 100.00
otbn_dmem_err 10.000s 18.781us 1 1 100.00
otbn_zero_state_err_urnd 13.000s 26.866us 1 1 100.00
otbn_illegal_mem_acc 7.000s 18.655us 1 1 100.00
otbn_sec_cm 414.000s 4410.725us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 414.000s 4410.725us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 10.000s 101.538us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 9.000s 66.188us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 8.000s 225.632us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 26.000s 184.159us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 26.000s 184.159us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 57.473us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 414.000s 4410.725us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 414.000s 4410.725us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 12.000s 58.486us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 414.000s 4410.725us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 414.000s 4410.725us 1 1 100.00
sec_cm_loop_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 7.000s 28.170us 0 1 0.00
sec_cm_call_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 7.000s 28.170us 0 1 0.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 7.000s 12.637us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 101.538us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 101.538us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 10.000s 101.538us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 56.000s 728.168us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 10.000s 101.538us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 10.000s 101.538us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 29.000s 235.867us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 10.000s 101.538us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 414.000s 4410.725us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 269.000s 4458.917us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 72353562646512045288019572285052712848109605656791475132846589016508100166338 167
UVM_INFO @ 4458916824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_stack_addr_integ_chk 4882899672480641011663085952970858288244803544993933170299344101962017364457 115
UVM_ERROR @ 28169698 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 28169698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---