Simulation Results: pwrmgr

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.70 %
  • code
  • 91.28 %
  • assert
  • 98.96 %
  • func
  • 96.87 %
  • line
  • 99.09 %
  • branch
  • 96.38 %
  • cond
  • 95.76 %
  • toggle
  • 91.15 %
  • FSM
  • 74.00 %
Validation stages
V1
100.00%
V2
80.00%
V2S
81.82%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.800s 27.684us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.720s 51.405us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.620s 33.399us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.080s 711.166us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.800s 52.763us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.120s 102.558us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.620s 33.399us 1 1 100.00
pwrmgr_csr_aliasing 0.800s 52.763us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.690s 183.808us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.690s 183.808us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.750s 41.222us 1 1 100.00
pwrmgr_lowpower_invalid 0.770s 115.371us 1 1 100.00
reset 0 2 0.00
pwrmgr_reset 0.920s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 3600.025s 0.000us 0 1 0.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 0.920s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.730s 125.205us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.860s 314.629us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.730s 121.609us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 10800.034s 0.000us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.680s 20.722us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.000s 25.199us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.000s 25.199us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.720s 51.405us 1 1 100.00
pwrmgr_csr_rw 0.620s 33.399us 1 1 100.00
pwrmgr_csr_aliasing 0.800s 52.763us 1 1 100.00
pwrmgr_same_csr_outstanding 0.800s 40.712us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.720s 51.405us 1 1 100.00
pwrmgr_csr_rw 0.620s 33.399us 1 1 100.00
pwrmgr_csr_aliasing 0.800s 52.763us 1 1 100.00
pwrmgr_same_csr_outstanding 0.800s 40.712us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
pwrmgr_tl_intg_err 3600.024s 0.000us 0 1 0.00
pwrmgr_sec_cm 1.280s 359.016us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.280s 359.016us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.280s 359.016us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 3600.024s 0.000us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.650s 1309.396us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.730s 125.205us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.960s 1292.233us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.920s 100.997us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.550s 39.563us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.280s 359.016us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.280s 359.016us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.280s 359.016us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.580s 130.293us 1 1 100.00
sec_cm_main_pd_rst_local_esc 0 1 0.00
pwrmgr_glitch 3600.028s 0.000us 0 1 0.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.170s 213.116us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.620s 33.399us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.620s 33.399us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.710s 1253.857us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 3600.025s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 5 test runs
pwrmgr_glitch 77020065370965194165353865887654960730300136526807217787605392179194544858895 None
pwrmgr_reset_invalid 33576459685242815110421636550060250188613326969173697628337485365037969626971 None
pwrmgr_tl_intg_err 39180585745350158674598863515043460035053836204383449946537937094259033931127 None
pwrmgr_stress_all_with_rand_reset 48405137645592519123493067948230619079619908802055995433123253169872801217873 None
pwrmgr_stress_all 14215492586827963062062078570765808496714436890369518782874473058814405660265 None
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 65956768423025880493518857827793054743693087963085167292162553646677661411146 159
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---