Simulation Results: rom_ctrl/32kb

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.42 %
  • code
  • 97.00 %
  • assert
  • 97.68 %
  • func
  • 97.59 %
  • line
  • 99.07 %
  • branch
  • 99.27 %
  • cond
  • 98.07 %
  • toggle
  • 95.28 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.400s 473.801us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.590s 130.522us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 1.750s 84.882us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.180s 129.885us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 1.850s 96.927us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 1.970s 67.895us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 1.750s 84.882us 1 1 100.00
rom_ctrl_csr_aliasing 1.850s 96.927us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 1.840s 49.342us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 1.950s 57.603us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 1.570s 3.984us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.910s 396.307us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.500s 686.655us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.280s 51.813us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.560s 752.693us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.560s 752.693us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.590s 130.522us 1 1 100.00
rom_ctrl_csr_rw 1.750s 84.882us 1 1 100.00
rom_ctrl_csr_aliasing 1.850s 96.927us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.580s 68.670us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.590s 130.522us 1 1 100.00
rom_ctrl_csr_rw 1.750s 84.882us 1 1 100.00
rom_ctrl_csr_aliasing 1.850s 96.927us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.580s 68.670us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.290s 14768.718us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 7.060s 176.382us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 201.290s 1143.144us 1 1 100.00
rom_ctrl_tl_intg_err 21.870s 140.067us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 201.290s 1143.144us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 201.290s 1143.144us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.290s 14768.718us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.290s 14768.718us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.290s 14768.718us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.290s 14768.718us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.290s 14768.718us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 201.290s 1143.144us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 201.290s 1143.144us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.400s 473.801us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.400s 473.801us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.400s 473.801us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 21.870s 140.067us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.290s 14768.718us 1 1 100.00
rom_ctrl_kmac_err_chk 5.500s 686.655us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.290s 14768.718us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.290s 14768.718us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.290s 14768.718us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 7.060s 176.382us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 201.290s 1143.144us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 236.840s 4902.823us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 23673772532953967205234449707267770944019196971787618271251889822487444658475 85
UVM_INFO @ 3983967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---