Simulation Results: rom_ctrl/64kb

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.58 %
  • code
  • 92.82 %
  • assert
  • 96.81 %
  • func
  • 97.11 %
  • line
  • 98.94 %
  • branch
  • 98.55 %
  • cond
  • 97.92 %
  • toggle
  • 95.34 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
77.78%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.480s 391.473us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.760s 57.184us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.400s 54.724us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.500s 65.786us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.100s 61.237us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.210s 99.633us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.400s 54.724us 1 1 100.00
rom_ctrl_csr_aliasing 3.100s 61.237us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.820s 49.238us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.930s 53.424us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 4.260s 11.014us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 13.660s 208.043us 1 1 100.00
kmac_err_chk 0 1 0.00
rom_ctrl_kmac_err_chk 3600.111s 0.000us 0 1 0.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.780s 93.359us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.040s 511.227us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.040s 511.227us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.760s 57.184us 1 1 100.00
rom_ctrl_csr_rw 3.400s 54.724us 1 1 100.00
rom_ctrl_csr_aliasing 3.100s 61.237us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.060s 103.105us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.760s 57.184us 1 1 100.00
rom_ctrl_csr_rw 3.400s 54.724us 1 1 100.00
rom_ctrl_csr_aliasing 3.100s 61.237us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.060s 103.105us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 83.960s 3909.183us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.850s 4155.518us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 432.020s 1511.266us 1 1 100.00
rom_ctrl_tl_intg_err 89.340s 200.711us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 432.020s 1511.266us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 432.020s 1511.266us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 83.960s 3909.183us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 83.960s 3909.183us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 83.960s 3909.183us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 83.960s 3909.183us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 83.960s 3909.183us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 432.020s 1511.266us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 432.020s 1511.266us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.480s 391.473us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.480s 391.473us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.480s 391.473us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 89.340s 200.711us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 83.960s 3909.183us 1 1 100.00
rom_ctrl_kmac_err_chk 3600.111s 0.000us 0 1 0.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 83.960s 3909.183us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 83.960s 3909.183us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 83.960s 3909.183us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.850s 4155.518us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 432.020s 1511.266us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 131.770s 4969.809us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 11341192856377581965305585494707995024822159603250280352681854546381187410175 85
UVM_INFO @ 11014439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
rom_ctrl_kmac_err_chk 56820679273267353404997342727067307766618580125897523091770186894758842235444 None