Simulation Results: rstmgr

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.84 %
  • code
  • 99.22 %
  • assert
  • 98.53 %
  • func
  • 95.77 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.47 %
  • toggle
  • 99.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.430s 264.703us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.120s 150.117us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.930s 98.068us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 9.070s 2828.505us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.690s 232.608us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.370s 193.865us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.930s 98.068us 1 1 100.00
rstmgr_csr_aliasing 1.690s 232.608us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.010s 140.939us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.620s 595.542us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.900s 79.195us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.800s 1182.614us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.800s 1182.614us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.800s 1182.614us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.800s 1182.614us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 30.380s 8720.100us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.810s 69.287us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.490s 122.870us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.490s 122.870us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.120s 150.117us 1 1 100.00
rstmgr_csr_rw 0.930s 98.068us 1 1 100.00
rstmgr_csr_aliasing 1.690s 232.608us 1 1 100.00
rstmgr_same_csr_outstanding 1.010s 128.440us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.120s 150.117us 1 1 100.00
rstmgr_csr_rw 0.930s 98.068us 1 1 100.00
rstmgr_csr_aliasing 1.690s 232.608us 1 1 100.00
rstmgr_same_csr_outstanding 1.010s 128.440us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 21.250s 17195.133us 1 1 100.00
rstmgr_tl_intg_err 3.150s 943.046us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 21.250s 17195.133us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 21.250s 17195.133us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.150s 943.046us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.460s 208.041us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 8.310s 2819.512us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.120s 302.327us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 21.250s 17195.133us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.930s 98.068us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.930s 98.068us 1 1 100.00