Simulation Results: rv_timer

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.82 %
  • code
  • 94.66 %
  • assert
  • 98.73 %
  • func
  • 97.06 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.010s 107.788us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.800s 25.945us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.640s 12.046us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.690s 90.535us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.060s 36.285us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.990s 116.700us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.640s 12.046us 1 1 100.00
rv_timer_csr_aliasing 1.060s 36.285us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 8.940s 36700.802us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 0.800s 160.511us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 776.460s 4045947.807us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 776.460s 4045947.807us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.970s 5845.982us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.640s 63.368us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.570s 17.831us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.260s 147.034us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.260s 147.034us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.800s 25.945us 1 1 100.00
rv_timer_csr_rw 0.640s 12.046us 1 1 100.00
rv_timer_csr_aliasing 1.060s 36.285us 1 1 100.00
rv_timer_same_csr_outstanding 0.690s 94.548us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.800s 25.945us 1 1 100.00
rv_timer_csr_rw 0.640s 12.046us 1 1 100.00
rv_timer_csr_aliasing 1.060s 36.285us 1 1 100.00
rv_timer_same_csr_outstanding 0.690s 94.548us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.770s 433.280us 1 1 100.00
rv_timer_tl_intg_err 1.140s 436.830us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.140s 436.830us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.660s 111.875us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.840s 201.869us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 48.390s 6135.064us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 3739862142743790553967408248336734586020592174740514970048383698764192457257 81
UVM_INFO @ 111874573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 46214528945788013099133054051094471358012345181562359362718265638980758002652 81
UVM_INFO @ 201869391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---