Simulation Results: spi_device/1r1w

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.28 %
  • code
  • 91.27 %
  • assert
  • 95.15 %
  • func
  • 78.42 %
  • line
  • 98.84 %
  • branch
  • 98.11 %
  • cond
  • 95.90 %
  • toggle
  • 74.14 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 40.220s 10270.857us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.800s 46.353us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.210s 45.055us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 19.620s 8948.864us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.830s 1736.814us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.450s 184.003us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.210s 45.055us 1 1 100.00
spi_device_csr_aliasing 5.830s 1736.814us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.710s 13.802us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.690s 54.043us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.880s 44.772us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.710s 4.300us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.670s 3.179us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.760s 53.045us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.760s 53.045us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.930s 740.880us 1 1 100.00
spi_device_tpm_sts_read 0.800s 95.186us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 6.540s 530.873us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 6.180s 9795.712us 1 1 100.00
spi_device_flash_all 108.340s 131786.640us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.200s 2262.465us 1 1 100.00
spi_device_flash_all 108.340s 131786.640us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.200s 2262.465us 1 1 100.00
spi_device_flash_all 108.340s 131786.640us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 108.340s 131786.640us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 5.500s 556.638us 1 1 100.00
spi_device_flash_all 108.340s 131786.640us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 5.500s 556.638us 1 1 100.00
spi_device_flash_all 108.340s 131786.640us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 5.500s 556.638us 1 1 100.00
spi_device_flash_all 108.340s 131786.640us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 5.500s 556.638us 1 1 100.00
spi_device_flash_all 108.340s 131786.640us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 5.500s 556.638us 1 1 100.00
spi_device_flash_all 108.340s 131786.640us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.230s 294.623us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 7.660s 517.961us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 7.660s 517.961us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 7.660s 517.961us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 11.940s 15756.565us 1 1 100.00
spi_device_read_buffer_direct 2.890s 261.889us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 7.660s 517.961us 1 1 100.00
spi_device_flash_all 108.340s 131786.640us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 108.340s 131786.640us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 108.340s 131786.640us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.330s 201.373us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.330s 201.373us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 150.830s 69601.959us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 40.220s 10270.857us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 122.400s 22946.737us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 278.500s 26030.250us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.770s 44.054us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.960s 70.330us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.780s 239.804us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.780s 239.804us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.800s 46.353us 1 1 100.00
spi_device_csr_rw 1.210s 45.055us 1 1 100.00
spi_device_csr_aliasing 5.830s 1736.814us 1 1 100.00
spi_device_same_csr_outstanding 1.860s 129.024us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.800s 46.353us 1 1 100.00
spi_device_csr_rw 1.210s 45.055us 1 1 100.00
spi_device_csr_aliasing 5.830s 1736.814us 1 1 100.00
spi_device_same_csr_outstanding 1.860s 129.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.030s 92.031us 1 1 100.00
spi_device_tl_intg_err 16.150s 4012.674us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 16.150s 4012.674us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1661) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 96304929810711919701959419915338516911521762815091519296077604494213725515403 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 3191881 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 3191881 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1004])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 5999426119325874405736181227787025117003988731132476596808366230459309455260 76
UVM_ERROR @ 867695 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3b8 [1110111000] vs 0x0 [0])
UVM_ERROR @ 879695 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x399 [1110011001] vs 0x0 [0])
UVM_ERROR @ 937695 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x12f [100101111] vs 0x0 [0])
UVM_ERROR @ 979695 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x54 [1010100] vs 0x0 [0])