Simulation Results: spi_host

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.94 %
  • code
  • 91.18 %
  • assert
  • 96.41 %
  • func
  • 88.24 %
  • block
  • 96.83 %
  • line
  • 98.59 %
  • branch
  • 93.05 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 25.000s 984.955us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 9.000s 62.963us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 9.000s 21.186us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 9.000s 82.396us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 9.000s 32.697us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 9.000s 42.525us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 9.000s 21.186us 1 1 100.00
spi_host_csr_aliasing 9.000s 32.697us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 9.000s 47.098us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 9.000s 77.771us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 22.610us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 9.000s 35.139us 1 1 100.00
spi_host_error_cmd 9.000s 16.635us 1 1 100.00
spi_host_event 21.000s 1310.399us 1 1 100.00
clock_rate 0 1 0.00
spi_host_speed 28.000s 200000.000us 0 1 0.00
speed 0 1 0.00
spi_host_speed 28.000s 200000.000us 0 1 0.00
chip_select_timing 0 1 0.00
spi_host_speed 28.000s 200000.000us 0 1 0.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 72.000s 3755.697us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 153.728us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 21.581us 1 1 100.00
cpol_cpha 0 1 0.00
spi_host_speed 28.000s 200000.000us 0 1 0.00
full_cycle 0 1 0.00
spi_host_speed 28.000s 200000.000us 0 1 0.00
duplex 1 1 100.00
spi_host_smoke 25.000s 984.955us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 25.000s 984.955us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 16.000s 2731.697us 1 1 100.00
spien 1 1 100.00
spi_host_spien 4.000s 257.543us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 14.000s 1589.127us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 10.000s 363.521us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 9.000s 35.139us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 9.000s 18.426us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 9.000s 24.955us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 9.000s 44.249us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 9.000s 44.249us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 9.000s 62.963us 1 1 100.00
spi_host_csr_rw 9.000s 21.186us 1 1 100.00
spi_host_csr_aliasing 9.000s 32.697us 1 1 100.00
spi_host_same_csr_outstanding 9.000s 70.659us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 9.000s 62.963us 1 1 100.00
spi_host_csr_rw 9.000s 21.186us 1 1 100.00
spi_host_csr_aliasing 9.000s 32.697us 1 1 100.00
spi_host_same_csr_outstanding 9.000s 70.659us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 9.000s 113.619us 1 1 100.00
spi_host_sec_cm 1.000s 207.180us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 9.000s 113.619us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
spi_host_speed 91892616312137616532773277698224330655049226126559717140148960689025062528905 129
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---