Simulation Results: sram_ctrl/main

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.98 %
  • code
  • 94.32 %
  • assert
  • 97.83 %
  • func
  • 92.80 %
  • block
  • 93.47 %
  • line
  • 94.53 %
  • branch
  • 90.91 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 6.000s 2805.455us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 49.319us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 47.276us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 387.303us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 13.830us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 370.321us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 47.276us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 13.830us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 306.000s 26267.773us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 133.000s 6951.075us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 41.000s 11360.078us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 139.000s 3041.585us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 170.000s 4693.143us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 41.000s 35873.994us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 26.000s 5840.781us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 37.000s 6352.706us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 1096.602us 1 1 100.00
sram_ctrl_partial_access_b2b 201.000s 23748.518us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.000s 691.785us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 1338.278us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 768.954us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1158.678us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 347.293us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 380.000s 91325.008us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 47.272us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 78.334us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 78.334us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 49.319us 1 1 100.00
sram_ctrl_csr_rw 2.000s 47.276us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 13.830us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 128.104us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 49.319us 1 1 100.00
sram_ctrl_csr_rw 2.000s 47.276us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 13.830us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 128.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 10017.579us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 426.046us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 97.924us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 426.046us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 97.924us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1158.678us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1158.678us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 47.276us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 37.000s 6352.706us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 37.000s 6352.706us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 37.000s 6352.706us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 26.000s 5840.781us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 10017.579us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 2805.455us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 2805.455us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 37.000s 6352.706us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 426.046us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 26.000s 5840.781us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 426.046us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 426.046us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 6.000s 2805.455us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 426.046us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 61.000s 5289.163us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 57938376314410198867213905116618836409698326535781280738520631100021812600471 None
sram_ctrl_mubi_enc_err 26876785865486668765284662203106945900411515710690953257961885315441374151020 None