Simulation Results: sram_ctrl/ret

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.85 %
  • code
  • 81.69 %
  • assert
  • 97.67 %
  • func
  • 93.20 %
  • block
  • 92.12 %
  • line
  • 93.71 %
  • branch
  • 88.07 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 113.060us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 40.850us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 139.699us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 129.049us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.259us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 40.462us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 139.699us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.259us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 14.000s 739.498us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 6.000s 311.355us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 7.000s 385.290us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 222.000s 43890.567us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 8.000s 645.299us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 16.000s 639.772us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 8.000s 2100.899us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 4.000s 712.599us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 868.086us 1 1 100.00
sram_ctrl_partial_access_b2b 228.000s 18748.772us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 32.218us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 52.315us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 41.316us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 137.951us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 116.021us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 18.000s 1361.661us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 15.290us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 1112.314us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 1112.314us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 40.850us 1 1 100.00
sram_ctrl_csr_rw 1.000s 139.699us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.259us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 88.121us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 40.850us 1 1 100.00
sram_ctrl_csr_rw 1.000s 139.699us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.259us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 88.121us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 3309.066us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 532.399us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 788.343us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 532.399us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 788.343us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 137.951us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 137.951us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 139.699us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 4.000s 712.599us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 4.000s 712.599us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 4.000s 712.599us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 8.000s 2100.899us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 3309.066us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 113.060us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 113.060us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 4.000s 712.599us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 532.399us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 8.000s 2100.899us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 532.399us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 532.399us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 113.060us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 532.399us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 21.000s 1036.812us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 94903864463769265310889350378371002690182090240977932207184623189516802104288 None
sram_ctrl_mubi_enc_err 98301566826241646530409529807617807299389449195274991978001947358582919040941 None