Simulation Results: sysrst_ctrl

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.60 %
  • code
  • 94.27 %
  • assert
  • 94.73 %
  • func
  • 67.81 %
  • line
  • 97.69 %
  • branch
  • 97.81 %
  • cond
  • 95.10 %
  • toggle
  • 100.00 %
  • FSM
  • 80.77 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.570s 2127.848us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.600s 2463.088us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 4.270s 2178.849us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.580s 2543.914us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.280s 4027.593us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.060s 2037.308us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 80.130s 38860.342us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 6.000s 2334.122us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.140s 2085.488us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.060s 2037.308us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.000s 2334.122us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 148.960s 77286.175us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 24.210s 27089.244us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 8.390s 3653.985us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 3.100s 5779.476us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 2.910s 2523.380us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.190s 2098.682us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 3.290s 2618.018us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 3.140s 2610.231us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 3.030s 8270.311us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 14.860s 31458.100us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 211.590s 82708.002us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 2.890s 2020.316us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.080s 2045.910us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.170s 2240.483us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.170s 2240.483us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.280s 4027.593us 1 1 100.00
sysrst_ctrl_csr_rw 4.060s 2037.308us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.000s 2334.122us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 12.730s 4957.259us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.280s 4027.593us 1 1 100.00
sysrst_ctrl_csr_rw 4.060s 2037.308us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.000s 2334.122us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 12.730s 4957.259us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 39.730s 42034.380us 1 1 100.00
sysrst_ctrl_tl_intg_err 20.900s 42529.619us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 20.900s 42529.619us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.930s 6709.318us 1 1 100.00