Simulation Results: uart

 
19/08/2026 15:30:27 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.30 %
  • code
  • 92.22 %
  • assert
  • 98.56 %
  • func
  • 44.11 %
  • line
  • 99.48 %
  • branch
  • 97.90 %
  • cond
  • 96.85 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
86.36%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 3.280s 5598.201us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.720s 205.102us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.610s 11.663us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.020s 384.932us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.780s 16.091us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.670s 165.405us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.610s 11.663us 1 1 100.00
uart_csr_aliasing 0.780s 16.091us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 19.110s 39309.342us 1 1 100.00
parity 2 2 100.00
uart_smoke 3.280s 5598.201us 1 1 100.00
uart_tx_rx 19.110s 39309.342us 1 1 100.00
parity_error 2 2 100.00
uart_intr 10.630s 23705.976us 1 1 100.00
uart_rx_parity_err 22.190s 23899.310us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 19.110s 39309.342us 1 1 100.00
uart_intr 10.630s 23705.976us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 22.210s 37661.886us 1 1 100.00
fifo_overflow 0 1 0.00
uart_fifo_overflow 85.880s 83594.510us 0 1 0.00
fifo_reset 1 1 100.00
uart_fifo_reset 7.440s 29348.928us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 10.630s 23705.976us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 10.630s 23705.976us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 10.630s 23705.976us 1 1 100.00
perf 1 1 100.00
uart_perf 72.260s 15324.698us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 4.400s 3776.529us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 4.400s 3776.529us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 6.230s 6373.849us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 4.380s 3690.445us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 11.390s 6973.921us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 4.940s 4209.627us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 237.760s 127115.476us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 351.190s 143625.291us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.600s 24.367us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.660s 17.967us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.570s 47.777us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.570s 47.777us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.720s 205.102us 1 1 100.00
uart_csr_rw 0.610s 11.663us 1 1 100.00
uart_csr_aliasing 0.780s 16.091us 1 1 100.00
uart_same_csr_outstanding 0.760s 41.504us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.720s 205.102us 1 1 100.00
uart_csr_rw 0.610s 11.663us 1 1 100.00
uart_csr_aliasing 0.780s 16.091us 1 1 100.00
uart_same_csr_outstanding 0.760s 41.504us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.880s 830.394us 1 1 100.00
uart_tl_intg_err 1.200s 56.639us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.200s 56.639us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 10.010s 1381.056us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:444) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty 1 test run
uart_fifo_overflow 11496293153937722460278553965778352585696462596143571681978745902036360133116 80
UVM_INFO @ 47172472626 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 1/5
UVM_INFO @ 48916122626 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 2/5
UVM_INFO @ 49172722626 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 3/5
UVM_INFO @ 81361497626 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 4/5
UVM_ERROR (uart_scoreboard.sv:390) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 61853773202981980877412503500969358319047036780245241425548657953586993340224 84
UVM_ERROR @ 5298368909 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 5346908909 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 5353488909 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 5353518909 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (99 [0x63] vs 93 [0x5d]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_stress_all 108012329779571526421615987181849989970996151926692139998553803772754514494993 93
UVM_ERROR @ 141651275242 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 141651330798 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 239 [0xef]) reg name: uart_reg_block.rdata
UVM_ERROR @ 141862721378 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 142008333654 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5, clk_pulses: 0